Philips Semiconductors
I2C-bus autosync deflection controller for
PC monitors
Product specification
TDA4856
SYMBOL
PARAMETER
CONDITIONS
Phase adjustments and corrections via PLL1 and PLL2
HPOS
horizontal position (referenced register HPOS = 0
to horizontal period)
register HPOS = 127
register HPOS = 255
HPINBAL
horizontal pin unbalance
correction via HPLL2
(referenced to horizontal
period)
register HPINBAL = 0;
note 6
register HPINBAL = 63;
note 6
register HPINBAL = 32;
note 6
HPARAL
horizontal parallelogram
correction (referenced to
horizontal period)
register HPARAL = 0;
note 6
register HPARAL = 63;
note 6
register HPARAL = 32;
note 6
HMOIRE
HMOIREoff
relative modulation of
horizontal position by
1⁄2 horizontal frequency;
phase alternates with
1⁄2 vertical frequency
moire cancellation off
register HMOIRE = 0;
control bit MOD = 0
register HMOIRE = 63;
control bit MOD = 0
control bit MOD = 1
PLL2 phase detector: pins HFLB and HPLL2
φPLL2
PLL2 control (advance of
maximum advance;
horizontal drive with respect to register HPINBAL = 32;
middle of horizontal flyback) register HPARAL = 32
minimum advance;
register HPINBAL = 32;
register HPARAL = 32
Ictrl(PLL2)
ΦPLL2
PLL2 control current
relative sensitivity of PLL2
phase shift related to horizontal
period
VPROT(HPLL2)(max) maximum voltage for PLL2
protection mode/soft start
Ich(HPLL2)
charge current for external
capacitor during soft start
VHPLL2 < 3.7 V
Idch(HPLL2)
discharge current for external VHPLL2 < 3.7 V
capacitor during soft down
MIN. TYP. MAX. UNIT
−
−13 −
%
−
0
−
%
−
13
−
%
−
−1.2 −
%
−
1.2
−
%
−
0.02 −
%
−
−1.2 −
%
−
1.2
−
%
−
0.02 −
%
−
0
−
%
−
0.07 −
%
−
0
−
%
36
−
−
%
−
7
−
%
−
75
−
µA
−
28
−
mV/%
−
4.6
−
V
−
1
−
µA
−
−1
−
µA
2003 Sep 30
18