SY69753AL(2006) Просмотр технического описания (PDF) - Micrel
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SY69753AL Datasheet PDF : 13 Pages
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Micrel, Inc.
SY69753AL
Pin Description
Inputs
Pin Number
2
3
5
26
32
25
16
Pin Name
RDINP
RDINN
REFCLK
CD
DIVSEL1
DIVSEL2
CLKSEL
Type
Differential
PECL
TTL Input
PECL Input
TTL Input
TTL Input
Pin Name
Serial Data Input: These built-in line receiver inputs are connected to the differential receive
serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data
(RDOUT) information.
Reference Clock: This input is used as the reference for the internal frequency synthesizer
and the "training" frequency for the receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
Carrier Detect: This input controls the recovery function of the Receive PLL and can be driven
by the carrier detect output of optical modules or from external transition detection circuitry.
When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a
constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output
LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency
generated from REFCLK.
Divider Select: These inputs select the ratio between the output clock frequency
(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency
Selection” table.
Clock Select: This input is used to select either the recovered clock of the receiver PLL
(CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
Outputs
Pin Number
31
23
24
20
21
18
17
9
10
14
15
Pin Name
LFIN
RDOUTN
RDOUTP
RCLKN
RCLKP
TCLKP
TCLKN
PLLSP
PLLSN
PLLRN
PLLRP
Type
TTL Output
Differential
PECL
Differential
PECL
Differential
PECL
Pin Name
Link Fault Indicator: This output indicates the status of the input data stream RDIN. Active
HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming
data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the
Receive PLL (1000ppm) and will be alternating if not. LFIN is an asynchronous output.
Receive Data Output: These ECL 100K outputs represent the recovered data from the input
data stream (RDIN). This recovered data is specified against the rising edge of RCLK.
Clock Output: These ECL 100K outputs represent the recovered clock used to sample the
recovered data (RDOUT).
Clock Output: These ECL 100K outputs represent either the recovered clock (CLKSEL =
HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency
synthesizer (CLKSEL = LOW).
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.
Power and Ground
Pin Number
27, 28
29
30
19, 22
Pin Name
VCC
VCCA
VCCO
Type
Pin Name
Power Supply.(1)
Analog Power Supply Voltage.(1)
Output Supply Voltage.(1)
12, 13
GND
Ground.
1, 4, 6, 7, 8
NC
No connect.
11
GNDA
Analog Ground.
Note:
1. VCC, VCCA, VCCO must be the same value.
November 2006
3
M9999-111406-D
hbwhelp@micrel.com or (408) 955-1690
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