STK672-340-E Просмотр технического описания (PDF) - SANYO -> Panasonic

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STK672-340-E

Two-Phase Stepping Motor Driver (Square Wave Drive) Output Current 2.2A

SANYO -> Panasonic 

• Motor current peak value IOH setting

IOH

STK672-340-E

0

IOH = Vref ÷ Rs

Vref = (RO2 ÷ (RO1 + RO2)) × 5V (or 3.3V)

Rs is the hybrid IC internal current detection resistor.

In the STK672-330-E (and STK672-350-E) Rs is 0.195Ω.

(In the STK672-340-E and STK672-360-E, Rs is 0.14Ω.)

ITF02173

Input Pin Functions

Pin Name

Pin No.

Function

Input Conditions When Operating

CLOCK

9

Reference clock for motor phase current switching

Operates on the rising edge of the signal

MODE

8

Excitation mode selection

Low: 2-phase excitation

High: 1-2 phase excitation

CWB

10

Motor direction switching

Low: CW (forward)

High: CCW (reverse)

RESETB

11

System reset and A, AB, B, and BB outputs cutoff.

A reset is applied by a low level

Applications must apply a reset signal for at least 10μs

when VDD is first applied.

ENABLE

12

The A, AB, B, and BB outputs are turned off, and after

The A, AB, B, and BB outputs are turned off by a low-

operation is restored by returning the ENABLE pin to the

level input.

high level, operation continues with the same excitation

timing as before the low-level input.

(1) A simple reset function is formed from D1, CO4, RO3, and RO4 in this application circuit. With the CLOCK input

held low, when the 5V supply voltage is brought up a reset is applied if the motor output phases A and BB are

driven. If the 5V supply voltage rise time is slow (over 50ms), the motor output phases A and BB may not be driven.

Increase the value of the capacitor CO4 and check circuit operation again.

(2) See the timing chart for the concrete details on circuit operation.

Usage Notes

1. STK672-340-E input signal functions and timing (Specifications common to the STK672-330-E as well)

(All inputs have no internal pull-up resistor.)

[RESETB and CLOCK (Input signal timing when power is first applied)]

As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the

F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10μs, as shown below.

The capacitor CO4, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the

RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application must

have the timing shown in figure 1.

Rise of the 5V supply voltage

RESETB signal input

CLOCK signal

At least 10μs

At least 5μs

Figure 1 RESETB and CLOCK Signals Input Timing

ITF02174

No.A1254-5/13

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