ST7036 Просмотр технического описания (PDF) - Unspecified

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производитель

ST7036

Dot Matrix LCD Controller/Driver

Unspecified 

ST7036

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

not acknowledge

acknowledge

1

2

8

9

S

START

condition

clock pulse for

acknowledgement

Fig .4 Acknowledgement on the IIC Interface

I2C Interface protocol

The ST7036 supports command, data write addressed slaves on the bus.

Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Four 7-bit slave

addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.

The I2C Interface protocol is illustrated in Fig.5.

The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After

acknowledgement, one or more command words follow which define the status of the addressed slaves.

A command word consists of a control byte, which defines Co and RS, plus a data byte.

The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a

cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command

or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,

depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set

to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is

automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to

logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received

commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C

INTERFACE-bus master issues a STOP condition (P).

V1.1

16/72

2003/12/24

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