ST16C2550CQ48 Просмотр технического описания (PDF) - Exar Corporation
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ST16C2550CQ48 Datasheet PDF : 39 Pages
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ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
40-PDIP
PIN #
44-PLCC
PIN #
48-TQFP
PIN #
DATA BUS INTERFACE
A2
26
29
26
A1
27
30
27
A0
28
31
28
D7
8
D6
7
D5
6
D4
5
D3
4
D2
3
D1
2
D0
1
9
3
8
2
7
1
6
48
5
47
4
46
3
45
2
44
IOR#
21
24
19
IOW#
18
20
15
CSA#
14
16
10
CSB#
15
17
11
INTA
30
33
30
INTB
29
32
29
TXRDYA#
-
RXRDYA#
-
1
43
34
31
xr
REV. 4.4.0
TYPE
DESCRIPTION
I Address data lines [2:0]. These 3 address lines select one
of the internal registers in UART channel A/B during a
data bus transaction.
IO Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
I Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines.
I UART channel A select (active low) to enable UART
channel A in the device for data bus operation.
I UART channel B select (active low) to enable UART
channel B in the device for data bus operation.
O UART channel A Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
O UART channel B Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTB is set to the active mode and OP2B# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
O UART channel A Transmitter Ready (active low). The out-
put provides the TX FIFO/THR status for transmit channel
A. See Table 2. If it is not used, leave it unconnected.
O UART channel A Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
A. See Table 2. If it is not used, leave it unconnected.
4
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