SPCA514A Просмотр технического описания (PDF) - Unspecified

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SPCA514A

Digital Audio USB Controller

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SPCA514A

3.8. SPI interface

3.8.1 SPI interface to the Serial flash memory

The SPCA514A supports an SPI serial interface to access the SPI-type serial flash

memory. Both SPI mode 0 and SPI mode 3 are supported. The serial clock frequency is

adjustable from 12 MHz to 3 MHz. The CPU writes data to the serial flash memory via the

TXport (register 8230) and read data from the flash memory via the RXport and PRXport.

Reading data from the PRXport will invoke a sequence of serial clocks to pre-fetch the next

byte of data. Reading data from the RXport merely gets the data that is already received

and latched in the SPCA514A. Each read sequence starts with a dummy read to the

PRXport, followed by multiple read from the PRXport, and finally end up with a read to the

RXport. Note that the data read by the first dummy read to the PRXport should be

discarded. Each time before the CPU write to the TXport or read from the PRXport, the

CPU must wait until the SPI interface is ready. This could be achieved by polling the status

bit (FMSIbusy, register 0X823B bit 0) each time before read or write.

When data is written into the spi-interface serial flash memory or read from them, a 16

bit CRC codes are generated automatically by the SPCA514A. For every 256 bytes of data,

16 bits of CRC codes are generated (access inverse of low byte CRC code via register

0x82b6, inverse of high byte CRC code via register 0x82b7). The CRC codes are

generated automatically when the CPU read/write the data port. The CRC code can be

cleared each time a new page is written to or read from the spi-interface serial flash

memory. To clear the CRC code, write 1 to register 0X82a5 bit0.

3.8.2 Next flash serial interface control

For the Next flash serial interface, the CPU has to control the output enable of the

serial data bit because the data pin is bi-directional. Also, the CPU has to explicitly start

and stop the transfer in order to control the status of the clock pin. There are 2 extra ports

for the CPU to read. The first one is PRX1 port. After this port is read, the SPCA514A

assert a signal clock and force the clock pin stay at high state. The second port is PRX7

port. After this port is read, the SPCA514A will assert the next seven clocks to complete the

byte read. This special timing is required by the Next flash memory. The CPU should wait

for 30 to 100 us between reading PRX1 and PRX7. Please reference to the Next flash

data sheet for the timing requirement.

 



  

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