SP674AB Просмотр технического описания (PDF) - Signal Processing Technologies

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SP674AB

12–Bit Sampling A/D Converters

Signal Processing Technologies 

READ MODE TIMING

CE

CS

R/C

A0

STS

DB11–

DB0

tSSR

tSRR

tHSR

tHRR

tSAR

tHAR

HIGH

IMPEDANCE

tDD

DATA

VALID

tHD

tHL

CHARACTERISTICS

Typical @ 25˚C, VCC = +15V or +12V, VLOGIC = +5V, VEE = 0V, unless otherwise specified.

PARAMETER

tDD Access Time From CE2

tHD Data Valid After CE Low2

tHL Output Float Delay2

tSSR CS to CE Setup

tSRR R/C to CE Setup

tSAR A0 to CE Setup

tHSR CS Valid After CE Low

tHRR R/C High After CE Low

tHAR A0 Valid After CE Low

tHS STS Delay After Data Valid

MIN.

25

50

0

50

0

0

50

300

TYP.

0

0

0

50

MAX.

150

150

1000

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

CONDITIONS

NOTES:

1. Parameters guaranteed by design and sample tested.

2. Parameters 100% tested @ 25˚C on special orders.

Figure 11. Read Mode Timing

15

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