TDA7421 Просмотр технического описания (PDF) - STMicroelectronics

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TDA7421

AM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONS

STMicroelectronics 

TDA7421

ADDRESS ORGANIZATION (PLL and IF Counter)

FUNCTION

SUBAD

PLL CHARGE PUMP 00H

PLL COUNTER

01H

PLL COUNTER

02H

PLL REF

03H

COUNTER

PLL REF

04H

COUNTER

PLL LOCK

05H

DETECT

IFC REF COUNTER 06H

IFC REF COUNTER 07H

IFC CONTROL

08H

IFC CONTROL

09H

MSB

BIT 7

LPIN1/2

PC7

PC15

RC7

RC15

LDENA

IRC7

IFCM1

IFENA

IFS2

BIT 6

CURRH

PC6

PC14

RC6

RC14

-

IRC6

IFCM0

-

IFS1

BIT 5

B1

PC5

PC13

RC5

RC13

D3

IRC5

IRC13

-

IFS0

BIT 4

B0

PC4

PC12

RC4

RC12

D2

IRC4

IRC12

-

CF4

BIT 3

A3

PC3

PC11

RC3

RC11

D1

IRC3

IRC11

-

CF3

quency. In FM mode a 6.25 KHz, in AM mode a

1KHz signal is generated. This counter is fol-

lowed by an asynchronous divider to generate

several sampling times.

Charge Pump Logic

BIT 2

A2

PC2

PC10

RC2

RC10

D0

IRC2

IRC10

EW2

CF2

BIT 1

A1

PC1

PC9

RC1

RC9

PM1

IRC1

IRC9

EW1

CF1

LSB

BIT 0

A0

PC0

PC8

RC0

RC8

PM0

IRC0

IRC8

EW0

CF0

Intermediate Frequency Main Counter (IFMC)

This counter is a 13-21 bit synchronous autore-

load down-counter. Four bits are programmable

to have the possibility for an adjust to the fre-

quency of the IF filter.

The counter length is automatically adjusted to

the chosen sampling time and the counter mode.

At the start the counter will be loaded with a de-

fined value which is an equivalent to the divider

value (tsample fIF).

If a correct frequency is applied to the IF counter

frequency inputs IF-AM and IF-FM, at the end of

the sampling time the main counter is changing

its state from 0 to 1FFFFFH.

This is detected by a control logic. The frequency

range inside which a successful count results is

detected is adjustable setting bits EW 0, 1, 2.

Up-down counter filter

The information coming from the IF main counter

control logic is shifted into a 5 bit up down

counter circuit clocked by the sampling time sig-

nal. At the start (rising edge of the IFENA signal)

the counter is set to 10H and the SSTOP signal is

forced to "1".

Only when the counter reaches the value 10H -

step, SSTOP goes to "0".

SSTOP will be "1" again, if the counter reaches

the value 10h + step.

CURR HIGH

LOCKENA

LOCK

CHARGE PUMP

CURRENT

D96AU548

FM and AM operation (swallow mode)

REF OSC IN

AM IN

FM IN

I2C bus

REGISTER

fosc

R0 ...R15

DIVIDER

:R

I2C bus

REGISTER

PC0 ...PC4

COUNTER

A

(O/I)

PRESCALER

32/33

fref

PD

fsyn

I2C bus

REGISTER

PC5 ... P15

DIVIDER

:B

D96AU545

16/38

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