SL11RIDE Просмотр технического описания (PDF) - Cypress Semiconductor
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SL11RIDE Datasheet PDF : 27 Pages
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Parameter
VCC
tRPU
Vmax
VRH
treset
tioact
Description
Operating Voltage Range
Time Reset Pull up
Voltage reach max
Voltage Reset High
nRESET Pulse width
nRESET high to nRD
Note: Clock is 48 MHz nominal.
9.6 Reset Circuit
9&&
µ)
0&
3
*1'
Min.
150 ms
VDD – 0.7V
3.0V
16 clocks
16 clocks
SL11RIDE
Typical
Max.
5.5V
6/5,'( Microcontroller
5(6(7
Figure 9-1. Reset Circuit Sample
9.7 SL11RIDE PIO Read/Write Cycle
At power-up and during Read/Write Cycles, the SL11RIDE uses PIO mode 2 timing for the data transfer from/to device. See
chapter 10 in the section 10.2.2 of [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5) for more detail.
10.0 Appendix
This is a pin translation of SL11RIDE signals to 36, 44, 50, and 68 of the Storage Device Class, which is based on the latest AT
Attachment specification and Compact Flash Specification Version 1.4.
These signals connect directly to the ATAPI/IDE devices. If you intend to design for a long IDE cable, then you have to use RC
Termination. See [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5).
10.1 SL11RIDE Pin Translation: 36-Pin–40-Pin Signals
Table 10-1. 36-pin to 40-pin Interface Signals
SL11RIDE Signal
GND
nRESET
D8
D7
D9
D6
D10
36-Pin Signal
GND
RESET
D8
D7
D9
D6
D10
36-Pin
1
2
3
4
5
6
7
Translates
→
→
→
→
→
→
→
40-Pin
2
1
4
3
6
5
8
Document #: 38-08007 Rev. **
Page 17 of 27
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