ADV473KP135 Просмотр технического описания (PDF) - Analog Devices
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ADV473KP135 Datasheet PDF : 12 Pages
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ADV473
Analog Signal Interconnect
The ADV473 should be located as close as possible to the out-
put connectors to minimize noise pickup and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
For maximum performance, the analog outputs should each
have a 75 Ω load resistor connected to GND. The connection
between the current output and GND should be as close as pos-
sible to the ADV473 to minimize reflections.
For more information on circuit board design and layout, see
application note entitled “Design and Layout of a Video Graph-
ics System for Reduced EMI” available from Analog Devices,
Publication No. E1309-15-10/89.
0.1µF
0.1µF
POWER SUPPLY DECOUPLING
(0.1µF CAPACITOR FOR
EACH VREF GROUP)
+5V (VAA)
0.1µF
ANALOG POWER PLANE +5V (VAA)
+5V (VCC)
VAA
COMP
COMP
10µF
L1
(FERRITE
BEAD)
0.1µF
VREFOUT
VREFIN
0.1µF
RSET
140Ω
ADV473
RSET
IOR
IOG
IOB
GND
75Ω
CO-AXIAL CABLE
(75Ω)
75Ω
75Ω
75Ω
75
Ω
75Ω
BNC
CONNECTORS
MONITOR
(CRT)
COMPONENT
C1 – C5
C6
L1
R1, R2, R3
RSET
DESCRIPTION
0.1µF CERAMIC CAPACITOR
10µF TANTALUM CAPACITOR
FERRITE BEAD
75Ω 1% METAL FILM RESISTOR
1% METAL FILM RESISTOR
VENDOR PART NUMBER
ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
FAIR-RITE 2743001111
Package Thermal Considerations
In certain circumstances, the 135 MHz version of the ADV473
may require forced air cooling or the addition of a heatsink. The
68-pin PLCC has a heat resistance characteristic as shown in
Table VIII.
It should be noted that information on Package Thermal Characteris-
tics published herein may not be the most up to date at the time of
reading this. Advances in packaging technology will inevitably lead
to improvements in thermal data. Please contact your local sales office
for the most up-to-date information.
Table VIII. Thermal Resistance vs. Airflow
Air Velocity
(Linear Feet/Min) 0 (Still Air) 50
100 200
θJA (°C/W)
32
26 19 16
9
10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Leaded Chip Carrier
(P-68A)
0.995 (25.27)
0.885 (22.48) SQ
PIN 1
IDENTIFIER
61
60
0.175 (4.45)
0.169 (4.29)
0.050
(1.27)
TYP
0.925 (23.50)
0.895 (22.73)
TOP VIEW
0.019 (0.48)
0.017 (0.43)
26
27
0.954 (24.23)
0.950 (24.13) SQ
44
43
0.029 (0.74)
0.027 (0.69)
0.104 (2.64) TYP
Figure 8. Typical Connection Diagram (Internal Voltage
Reference)
–12–
REV. A
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