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SI4702-C19 Просмотр технического описания (PDF) - Silicon Laboratories

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SI4702-C19 Datasheet PDF : 46 Pages
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Si4702/03-C19
Table 5. Reset Timing Characteristics (Busmode Select Method 2)1,2,3
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
GPIO1 and GPIO3 Setup to RST
tSRST2
GPIO3 = 1
30
ns
GPIO1 and GPIO3 Hold from RST
tHRST2
30
ns
Notes:
1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
tSRST2 tHRST2
RST 70%
30%
GPIO3 70%
30%
GPIO1 70%
30%
Figure 2. Reset Timing Parameters for Busmode Select Method 2 (GPIO3 = 1)
Rev. 1.1
7

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