R5F7083(2007) Просмотр технического описания (PDF) - Renesas Electronics

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производитель

R5F7083
(Rev.:2007)

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

8.2.10 Bus Function Extending Register (BSCEHR) ...................................................... 183

8.3 Activation Sources ............................................................................................................. 184

8.4 Location of Transfer Information and DTC Vector Table ................................................. 184

8.5 Operation ........................................................................................................................... 189

8.5.1 Transfer Information Read Skip Function ............................................................ 194

8.5.2 Transfer Information Writeback Skip Function .................................................... 195

8.5.3 Normal Transfer Mode ......................................................................................... 195

8.5.4 Repeat Transfer Mode........................................................................................... 196

8.5.5 Block Transfer Mode ............................................................................................ 198

8.5.6 Chain Transfer ...................................................................................................... 199

8.5.7 Operation Timing.................................................................................................. 201

8.5.8 Number of DTC Execution Cycles ....................................................................... 204

8.5.9 DTC Bus Release Timing ..................................................................................... 206

8.5.10 DTC Activation Priority Order ............................................................................. 209

8.6 DTC Activation by Interrupt.............................................................................................. 210

8.7 Examples of Use of the DTC ............................................................................................. 211

8.7.1 Normal Transfer Mode ......................................................................................... 211

8.7.2 Chain Transfer when Counter = 0......................................................................... 211

8.8 Interrupt Sources................................................................................................................ 213

8.9 Usage Notes ....................................................................................................................... 213

8.9.1 Module Standby Mode Setting ............................................................................. 213

8.9.2 On-Chip RAM ...................................................................................................... 213

8.9.3 DTCE Bit Setting.................................................................................................. 213

8.9.4 Chain Transfer ...................................................................................................... 213

8.9.5 Transfer Information Start Address, Source Address,

and Destination Address ....................................................................................... 214

8.9.6 Access to DMAC or DTC Registers through DTC............................................... 214

8.9.7 Notes on IRQ Interrupt as DTC Activation Source .............................................. 214

8.9.8 Notes on SCI and SCIF as DTC Activation Sources ............................................ 214

8.9.9 Clearing Interrupt Source Flag.............................................................................. 214

8.9.10 Conflict between NMI Interrupt and DTC Activation .......................................... 215

8.9.11 Operation when a DTC Activation Request is Cancelled While in Progress........ 215

Section 9 Bus State Controller (BSC)................................................................217

9.1 Features.............................................................................................................................. 217

9.2 Input/Output Pins ............................................................................................................... 220

9.3 Area Overview ................................................................................................................... 222

9.3.1 Area Division........................................................................................................ 222

9.3.2 Address Map ......................................................................................................... 222

9.4 Register Descriptions ......................................................................................................... 241

Rev. 3.00 May 17, 2007 Page xiii of lviii

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