SH7059 Просмотр технического описания (PDF) - Renesas Electronics
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SH7059 Datasheet PDF : 1042 Pages
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Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
5.1.3 Related Register
Table 5.2 CPG Register
74
5.2.1 Frequency Ranges
Table 5.3 Input Frequency and Operating Frequency
75
The internal clock signal (φ), with frequency either four or
eight times the frequency of the clock signal input from the
EXTAL pin, is mainly supplied to the bus master modules
such as CPU, FPU, and DMAC.
SH7058S/SH7059
5.1.3 Related Register
Table 5.2 CPG Register
Deleted
5.2.1 Frequency Ranges
Table 5.2 Input Frequency and Operating Frequency
Table amended
Description of x 4 version (PLL Multiplication Factor)
deleted
Description amended
The internal clock signal (φ), with frequency eight times
the frequency of the clock signal input from the EXTAL pin,
is mainly supplied to the bus master modules such as
CPU, FPU, and DMAC.
Figure 5.2 Frequencies and Phases of Clock Signals
5.2.2 Clock Selection
75,76
5.2.3 Notes on Register Access
Figure 5.3 Writing to SYSCR2
76, 77
5.4 Oscillation Stop Detection Function
79 - 81
6.1.1Types of Exception Processing and Priority
Table 6.1 Types of Exception Processing and Priority
Order
85
Exception Source
Interrupt On-chip peripheral modules:
Serial communication interface (SCI)
Controller area network 0 (HCAN0)
Figure 5.2 Frequencies and Phases of Clock Signals
Figure amended
Description of internal clock (φ) = input clock x 4 deleted
5.2.2 Clock Selection
Deleted
5.2.3 Notes on Register Access
Figure 5.3 Writing to SYSCR2
Deleted
Deleted
6.1.1Types of Exception Processing and Priority
Table 6.1 Types of Exception Processing and Priority
Order
On-chip peripheral modules: Synchronous serial
communication unit (SSU) added
Exception
Interrupt
Source
On-chip peripheral modules:
Serial communication interface (SCI)
Synchronous serial communication unit (SSU)
Controller area network 0 (HCAN0)
6.2.2 Power-On Reset
6.2.2 Power-On Reset
90
Power-On Reset by Means of RES Pin: When the RES pin
is driven low, the chip enters the power-on reset state. To
reliably reset the chip, the RES pin should be kept at the
low level for at least the duration of the oscillation settling
time at power-on or when in standby mode (when the clock
is halted), or at least 20 tcyc when the clock is running. In the
power-on reset state, the CPU's internal state and all the
on-chip peripheral module registers are initialized.
Description amended
Power-On Reset by Means of RES Pin: When the RES pin
is driven low, the chip enters the power-on reset state. To
reliably reset the chip, the RES pin should be kept at the
low level for at least the duration of the oscillation settling
time at power-on or when in standby mode (when the clock
is halted), or at least 10 tcyc when the clock is running. In the
power-on reset state, the CPU’s internal state and all the
on-chip peripheral module registers are initialized.
6.4.1 Interrupt Sources
6.4.1 Interrupt Sources
Table 6.7 Interrupt Sources
Table 6.7 Interrupt Sources
93
Synchronous serial communication unit (SSU) added
Type
On-chip peripheral module
Request Source
Synchronous communication unit (SSU)
Number of Sources
6
Rev.3.00 Mar. 12, 2008 Page xii of xc
REJ09B0177-0300
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