HD64F7018X20 Просмотр технического описания (PDF) - Renesas Electronics

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HD64F7018X20

Hitachi SuperH™ RISC engine

Renesas Electronics 

Section 2 CPU

2.1 Register Configuration

The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four

32-bit system registers.

2.1.1 General Registers (Rn)

The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for

data processing and address calculation. R0 is also used as an index register. Several instructions

have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving

and recovering the status register (SR) and program counter (PC) in exception processing is

accomplished by referencing the stack using R15. Figure 2.1 shows the general registers.

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0

R0*1

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15, SP (hardware stack pointer)*2

Notes: 1.

2.

R0 functions as an index register in the indirect indexed register addressing

mode and indirect indexed GBR addressing mode. In some instructions, R0

functions as a fixed source register or destination register.

R15 functions as a hardware stack pointer (SP) during exception processing.

Figure 2.1 General Registers

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