SH7014 Просмотр технического описания (PDF) - Renesas Electronics

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SH7014

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine family/SH7010 Series

Renesas Electronics 

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Page

13.4.8 A/D Conversion 392

Time

Table 13.7 A/D

Conversion Times

Table 13.8 Operating

Frequency and CKS Bit

Settings

13.6.5 A/D Conversion 394

Termination

(HD6417014R only)

14.1.3 Pin

399

Configuration

14.2.1 A/D Data

401

Register A to D (ADDRA

to ADDRD)

14.4.2 Scan Mode 409

(SCAN = 1)

14.5 Interrupt

414

15.4.1 Interrupt

427

Sources

Revision (See Manual for Details)

Note 2 amended

2. Table entries are for when PWR = 1. If 200 states have not

elapsed since the ADST bit has been set, no conversions

are done until after those 200 states have occurred.

When PWR = 0, add 200 states to the first A/D conversion

start delay time. When two or more conversions are

performed in succession, tcp is 20 cycles when CKS = 0,

and 40 cycles when CKS = 1.

Note added

Note: The indication "⎯" means the setting is not available.

Title amended

Description amended

The eight analog input pins are divided into two groups, with

analog input pins 0 to 3 (AN0 to AN3) comprising group 0, and

analog input pins 4 to 7 (AN4 to AN7) comprising group 1.

The AVCC and AVSS pins are for the mid-speed speed A/D

converter internal analog section power supply.

Description amended

A/D registers are special registers that read stored results of

A/D conversion in 16 bits. There are four registers: ADDRA to

ADDRD.

Description amended

An example of operation in scan mode when three channels of

group 0 (AN0 to AN2) are selected for A/D conversion is shown

in figure 14.4.

1. Set the operation mode to scan mode (SCAN = 1), set the

scan group to group 0 (CH2 = 0), set the analog channels to

AN0 to AN2 (CH1 = 1, CH0 = 0), and then start A/D

conversion (ADST = 1).

Description amended

The mid-speed A/D converter's interrupt source is summarized

in table 14.5.

When the DMAC are activated by an ADI interrupt, the ADF flag

of ADCSR is cleared to 0 by register access of A/D.

Title amended

Rev.5.00 Sep. 27, 2007 Page xv of xxxiv

REJ09B0398-0500

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