SH7054F Просмотр технического описания (PDF) - Renesas Electronics
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SH7054F Datasheet PDF : 919 Pages
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18.3.17 Port H Control Register (PHCR).......................................................................... 644
18.3.18 Port J IO Register (PJIOR) ................................................................................... 650
18.3.19 Port J Control Registers H and L (PJCRH, PJCRL) ............................................ 651
18.3.20 Port K IO Register (PKIOR) ................................................................................ 655
18.3.21 Port K Control Registers H and L (PKCRH, PKCRL) ........................................ 656
18.3.22 Port K Invert Register (PKIR).............................................................................. 660
Section 19 I/O Ports (I/O).................................................................................................. 661
19.1 Overview............................................................................................................................ 661
19.2 Port A................................................................................................................................. 662
19.2.1 Register Configuration ......................................................................................... 662
19.2.2 Port A Data Register (PADR) .............................................................................. 663
19.3 Port B ................................................................................................................................. 664
19.3.1 Register Configuration ......................................................................................... 664
19.3.2 Port B Data Register (PBDR)............................................................................... 665
19.4 Port C ................................................................................................................................. 666
19.4.1 Register Configuration ......................................................................................... 666
19.4.2 Port C Data Register (PCDR)............................................................................... 666
19.5 Port D................................................................................................................................. 668
19.5.1 Register Configuration ......................................................................................... 668
19.5.2 Port D Data Register (PDDR) .............................................................................. 669
19.6 Port E ................................................................................................................................. 670
19.6.1 Register Configuration ......................................................................................... 670
19.6.2 Port E Data Register (PEDR) ............................................................................... 671
19.7 Port F ................................................................................................................................. 673
19.7.1 Register Configuration ......................................................................................... 673
19.7.2 Port F Data Register (PFDR)................................................................................ 674
19.8 Port G................................................................................................................................. 676
19.8.1 Register Configuration ......................................................................................... 676
19.8.2 Port G Data Register (PGDR) .............................................................................. 676
19.9 Port H................................................................................................................................. 678
19.9.1 Register Configuration ......................................................................................... 679
19.9.2 Port H Data Register (PHDR) .............................................................................. 679
19.10 Port J.................................................................................................................................. 681
19.10.1 Register Configuration ......................................................................................... 681
19.10.2 Port J Data Register (PJDR) ................................................................................. 682
19.11 Port K................................................................................................................................. 683
19.11.1 Register Configuration ......................................................................................... 683
19.11.2 Port K Data Register (PKDR) .............................................................................. 684
19.12 POD (Port Output Disable) Control .................................................................................. 685
Section 20 ROM (SH7052F/SH7053F) ........................................................................ 687
20.1 Features.............................................................................................................................. 687
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