SERC816 Просмотр технического описания (PDF) - STMicroelectronics
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SERC816 Datasheet PDF : 23 Pages
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3.5.5 Read Access of Dual Port RAM
Figure 9. Read Access of Dual Port RAM
A10-0, BHEN,
MCSN0-1,
WRN (Motorola mode)
RDN
D15-0
BUSYN
tASU
tMRDD
tMBSY
tMBHD
SERCON816
tAHD
tRD1
tRDZ
Symbol
Parameter
Min.
Typ.
Max.
Unit
tASU Setup time A11-0, (Note 1)
10
ns
Setup time MCSN0-1, if both signals are activated
5
ns
simultaneously. (Note 1)
Setup time MCSN0-1, if one of these both signals is activated
0
ns
10 ns earlier. (Note 1)
Setup time BHEN, WRN (only Motorola mode), (Note 1)
0
ns
tAHD hold time A11-0, BHEN, MCSN0-1, WRN (only Motorola
0
ns
mode) to rising edge RDN (Intel Motorola mode with low
active strobe) or falling edge RDN (Motorola mode with high
active strobe)
tRDNCLK Cycle time of RAM read clock
SBAUD16 = 1 (fRDNCLK = fSCLK)
1 / fSCLK
SBAUD16 = 0 (fRDNCLK = 2 * fSCLK)
0.5 / fSCLK
tMRDD access time RDN to D15-0 valid
2 * tRDNCLK
ns
+ 30
tMBSY delay RDN to BUSYN low
15
ns
tMBHD Delay BUSYN high to D15-0 valid
2 * tRDNCLK
ns
+ 30
tRDZ Delay RDN to D15-0 high-Z
20
ns
tRD1 RDN and WRN high after end of read access
15
ns
Notes: 1. Setup time input signals to falling edge RDN (Intel or Motorola mode with low active strobe) or rising edge RDN (Motorola mode
with high active strobe)
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