SC508 Просмотр технического описания (PDF) - Semtech Corporation

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SC508

EcoSpeed® DC-DC Buck Controller with Integrated LDO

Semtech Corporation 

SC508/SC508A

Applications Information (continued)

The current limit schematic with the RLIM resistor is shown

in Figure 10.

the soft-start time (tSS). The calculation for the soft-start

time is shown by the following equation.

BST

DH

LX

ILIM

DL

PGND

VIN

Q1

CBST

RLIM

Q2

+

CIN

L

VOUT

D2

COUT

+

t SS

CSS u 1.5V

3PA

After the SS capacitor voltage reaches 1.5V, the SS capaci-

tor continues to charge until the SS voltage is equal to

67% of VDDA. At this time the Power Good monitor com-

pares the FB pin and sets the PGOOD output high (open

drain) if VOUT is in regulation. The time between VOUT

reaching the regulation point and the PGOOD output

going high is shown by the following equation.

Figure 10 — Valley Current Limit

Setting the valley current limit to 10A results in a peak

inductor current of 10A plus peak ripple current. In this

situation the average current through the inductor is 10A

plus one-half the peak-to-peak ripple current.

The RLIM value is calculated by the next equation.

5/,0

5'621 u ,/,0

ȝ$

The internal 10μA current source is temperature compen-

sated at 4100ppm in order to provide tracking with the

RDSON.

Soft-Start of PWM Regulator

The SC508 has a programmable soft-start time that is con-

trolled by an external capacitor at the SS pin. During the

soft-start time, the controller sources 3μA from the SS pin

to charge the capacitor. During the start-up process

(Figure 11), 40% of the voltage ramp at the SS pin is used

as the reference for the FB comparator. The PWM compara-

tor issues an on-time pulse when the FB voltage is less

than 40% of the SS voltage, which forces the output

voltage to follow the SS ramp. The output voltage reaches

regulation when the SS pin voltage exceeds 1.5V and the

FB reaches the 600mV threshold. The time between the

first LX pulse and VOUT reaching the regulation point is

W3*22'

&66 u ¨§  u 9''$  9 ¸·

ȝ$ © 

¹

The time from the rising edge of the EN pin to the PGOOD

output going high is shown by the following equation.

W(1B*22'

&66 u ¨§  u 9''$ ¸·

ȝ$ ©  ¹

After the Power Good Start-up Delay Time is completed,

the SS pin is internally pulled up to the VDDA supply.

The soft-start cycle and Power Good timing can be seen in

the Figure 11.

EN

CSS charging VSS = 1.5V

current 3uA

SS

VSS = 3.35V

VOUT in regulation

FB

tSS

PGOOD

tPGOOD

Figure 11 — Soft-start Cycle and Power Good timing

18

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