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SC4524C Просмотр технического описания (PDF) - Semtech Corporation

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SC4524C
Semtech
Semtech Corporation Semtech
SC4524C Datasheet PDF : 22 Pages
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SC4524C
Applications Information (Cont.)
The total power loss of the SC4524C is therefore
PTOTAL = PC + PSW + PBST = PQ
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
The temperature rise of the SC4524C is the product of the
total
power
dissipation
(see
previous
equation)
and
q
JA
V IN
(36oC/W), which is the thermal impedance from junction
to ambient for the SOIC-8 EDP package.
It is not recommended to operate the SC4524C above
125oC junction temperature. In the applications with high
input voltage and high output current, the switching
frequency may need to be reduced to meet the thermal
requirement.
VOUT
ZL
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4524C, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
Figure 9 — Pulse current Loop
Note: Heavy lines indicate the critical pulse current loop. The stray
inductance of this loop should be minimized
16

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