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SC2440

2.5 MHz Dual Switching Regulator with Integrated 2A Switches

Semtech Corporation 

SC2440

POWER MANAGEMENT

Applications Information

Minimum On Time Consideration

The operating duty cycle of a step-down switching

regulator with diode rectifier in continuous-conduction

mode (CCM) is given by

D2

=

3.3 + 0.45

13.2 + 0.45 − 0.25

=

0.28

Minimum On Time vs Temperature

130

D

=

VIN

VOUT

+ VD

+ VD

− VCESAT

120

(2)

110

vwohlteargeeVdCErSoATp

is the switch saturation voltage

across the rectifying diode.

and

VD

is

Duty cycle decreases with increasing

VIN

VOUT

ratio. In peak

current-mode control, the PWM modulating ramp is the

sensed current ramp of the power switch. This current

ramp is absent unless the switch is turned on. The

intersection of this ramp with the output of the voltage

feedback error amplifier determines the switch pulse

width. The propagation delay time required to

immediately turn off the switch after it is turned on is

the minimum switch on time (TON(MIN)). Closed-loop

measurement of the SC2440 with low

VOUT

VIN

ratios shows

that the minimum on time is about 105ns at room

tteemmppeerraatuturerec.oTeOfNfi(cMiIeN)ntal(sFoiguerxeh6ib).i

ts a

The

slight

power

positive

switch in

the SC2440 is either not turned on at all or for at least

TON(MIN).

If

the

required

switch

on

time

(=

D

f

)

is

shorter

than the minimum on time, the regulator will either skip

cycles or it will jitter.

Example: Determine the maximum operating frequency

of a dual 12V to 1.0V and 12V to 3.3V switching

regulator using the SC2440.

(ADu1ss20,sinu%ogmf(h2tinhig)ge.ht1hli.an0teVV),Datn=hde0.3c4.o53rVVre, scVopCEnoSvnATed=ritne0gr.s2d5ucVatynarnbadetiVocIsNa,=lcDu11l3aa.t2neddV

D1

=

1

13.2 +

+ 0.45

0.45 − 0.25

=

0.11

100

90

80

-40 -20

0 20 40 60

Temperature (°C)

80 100

Figure 6. Variation of Minimum On Time with

Temperature.

If the ambient temperature can be as high as 85°C, then

the maximum operating frequencies of the 1.0V and the

3.3V converters will be

D1

120ns

=

920KHz

and

D2

120ns

= 2.3MHz

respectively.

Channel frequency should be set below 920KHz to allow

margin for load transient.

Minimum Off Time Limitation

The PWM latch in Figure 2 is reset every period by the

clock. The clock also turns off the power transistor to

refresh the bootstrap capacitor. This minimum off time

limits the attainable duty cycle of the regulator at a given

switching frequency. Measurement shows that the power

transistor needs to be turned off for at least 120ns every

switching period to properly reset the latch and to refresh

the bootstrap capacitor. For a step-down converter, D

increases with increasing

VOUT

VIN

ratio. If the required duty

cycle is higher than the attainable maximum, then the

© 2005 Semtech Corp.

10

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