SAK-XC2765X-104FXXL Просмотр технического описания (PDF) - Infineon Technologies

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SAK-XC2765X-104FXXL

16-Bit CMOS Single-Chip Microcontrollers

Infineon Technologies 

XC2765X

XC2000 Family Derivatives / Base Line

General Device Information

Key to Pin Definitions

• Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated

register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to

1x00B, output O1 is selected by 1x01B, etc.

Output signal OH is controlled by hardware.

• Type: Indicates the pad type and its power supply domain (A, B, M, 1)

– St: Standard pad

– Sp: Special pad

– DP: Double pad - can be used as standard or high-speed pad

– In: Input only pad

– PS: Power supply pad

Table 5

Pin Definitions and Functions

Pin Symbol

Ctrl. Type Function

3 TESTM

I

In/B Testmode Enable

Enables factory test modes, must be held HIGH for

normal operation (connect to VDDPB).

An internal pullup device will hold this pin high

when nothing is driving it.

4 P7.2

O0 / I St/B Bit 2 of Port 7, General Purpose Input/Output

EMUX0

O1 St/B External Analog MUX Control Output 0 (ADC1)

CCU62_CCP I

OS0A

St/B CCU62 Position Input 0

TDI_C

I

St/B JTAG Test Data Input

5 TRST

I

In/B Test-System Reset Input

For normal system operation, pin TRST should be

held low. A high level at this pin at the rising edge

of PORST activates the XC2765X’s debug

system. In this case, pin TRST must be driven low

once to reset the debug system.

An internal pulldown device will hold this pin low

when nothing is driving it.

6 P7.0

O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output

T3OUT

O1 St/B GPT12E Timer T3 Toggle Latch Output

T6OUT

O2 St/B GPT12E Timer T6 Toggle Latch Output

TDO_A

OH / I St/B JTAG Test Data Output / DAP1 Input/Output

ESR2_1

I

St/B ESR2 Trigger Input 1

Data Sheet

13

V2.0, 2009-03

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