SAA7708H Просмотр технического описания (PDF) - Philips Electronics
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SAA7708H Datasheet PDF : 60 Pages
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Philips Semiconductors
Car Radio Digital Signal Processor
Preliminary specification
SAA7708H
10 FUNCTIONAL DESCRIPTION
10.1 Signal path for Level information
For FM weak signal processing, for AM and FM purposes (absolute level and multipath) a FM/AM Level input is
implemented (pin LEVEL). In the case of radio reception the clocking of the filters and the AD is based on a 38 kHz Fs
frequency. A DC input signal is converted by a bitstream first order Sigma-Delta AD converter followed by a decimation
filter.
The input signal has to be obtained from a radio part. The tuner must deliver the level information of either AM or FM to
the LEVEL pin.
10.1.1 THE VREFAD PIN
Via this pin the Midref voltage of the AD’s is filtered. This Midref voltage is used as reference of the LEVEL AD and half
supply reference of the two third order switch capacitor ADs. External capacitors (connected to VSSA1) prevents
crosstalk between the AD’s. This pin must also used in the application as reference for the inputs AM/AM_R, AM_L, ,
TAPE_L and TAPE_R (see Fig. 21).
10.2 Signal path of the third order switched capacitor AD’s.
10.2.1 THE FM MPX SIGNAL PATH
The CDSP has in total three analog audio source channels. One of the analog inputs is the FM_MPX signal. Selection
of this signal is achieved according Table 3. The multiplex FM signal is converted to the digital domain in SCAD1, a
bitstream third order switched capacitor AD converter. A decimation filter reduces the output of the AD to a lower sample
rate. From this filter the following signals are derived and are processed in the DSP.
The outputs from this signal path to the DSP which are all running on a sample frequency of 38 kHz are:
• Pilot presence indication: Pilot-I. This one bit signal is low for a pilot frequency deviation < 3 kHz and high for a pilot
frequency deviation > 3 kHz AND the FM MPX stereodecoder is locked on a pilot tone.
• ‘Left’ and ‘Right’ FM reception stereo signal: This is the 18 bit output of the stereo decoder after the matrix decoding
in ISN I2S format.This signal is fed via a muxer to a general I2S interface block that communicates with the DSP.
• A noise level information. This signal is derived from the first MPX decimation fiter via a wide band noise filter.
Detection is done with an envelope detector. This noise level is filtered in the DSP core and is used to optimize the FM
weak signal processing.
Normally the FM_MPX input and the FM_RDS input have the same source. If the FM input contains a stereo radio
channel, the pilot information is used to lock the clocking of the decimation filters of FM MPX and RDS path and also the
stereo decoder.
10.2.2 INPUT SENSITIVITY FOR FM AND RDS
The FM and RDS input sensitivity is designed for tuner front ends which deliver an output voltage of 200 mVrms at a
modulation depth of 22.5 kHz of a 1 kHz tone. In this case the I2C bit pcs_ad_sel must be ‘o’ and the SEL_FR switch is
also low. The MPX part of the FM_MPX signal will be processed via SCAD1, the RDS part is processed via SCAD2..
Another input sensitivity can be obtained by putting the pcs_ad_sel bit high. Biasing of this input must now take place
exterenally via high-ohmic resistors connected to the VREFAD pin. In this case the input sensitivity has increased from
200 mVrms to 65 mVrms at modulation depth of 22.5 kHz. Reduction of the input sensitivity can be obtained by an
external resistor tap consisting of an in the signal path placed series resistor and a resistor to VREFAD.
10.2.3 THE SIGNAL FLOW OF THE AM, CD ANALOG AND TAPE
The signal AM mono via the AM/AM_R input can be selected by the correct values of the I2C bits. There is also an option
available to connect a left and right signal to the chip. This can be for instance the AM-Right and AM-Left signal. The AM,
TAPE and CD inputs are buffered by an opamp to ensure a high ohmic input that makes external signal reduction
1998 May 19
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