SAA7185WP Просмотр технического описания (PDF) - Philips Electronics
Номер в каталоге
Компоненты Описание
производитель
SAA7185WP Datasheet PDF : 36 Pages
| |||
Philips Semiconductors
Digital Video Encoder (DENC2)
Preliminary specification
SAA7185
PINNING
SYMBOL
VSSD1
DP4
DP5
DP6
DP7
RCV1
RCV2
VSSD2
VP0
VP1
VP2
VP3
VP4
VP5
VP6
VP7
VDDD1
SEL_ED
VSSD3
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
VSSD4
RCM1
RCM2
KEY
OSD0
OSD1
OSD2
VSSD5
CDIR
VDDD2
PIN
DESCRIPTION
1 digital ground 1
2
3
Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
4
MPU interface. If it is LOW, they are the UV lines of the Video Port.
5
6 Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VS/FS/FSEQ signal.
7 Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides an HS/HREF/CBL signal.
8 digital ground 2
9
10
11
12 Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit
13 DIG-TV2 format is used, this is the Y data.
14
15
16
17 digital supply voltage 1
18 Select Encoder Data. Selects data either from MPEG port or from video port as encoder input.
19 digital ground 3
20
21
22
23
MPEG Port. It is an input for CCIR 656 style multiplexed YUV data.
24
25
26
27
28 digital ground 4
29 Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal.
30 Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder.
31 Key signal for OSD. It is active HIGH.
32
33 On-Screen Display data. This is the index for the internal OSD look-up table.
34
35 digital ground 5
36 Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC
and CREF are generated by the internal crystal oscillator.
37 digital supply voltage 2
1996 Jul 08
4
Share Link: 