S3C7235 Просмотр технического описания (PDF) - Samsung

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S3C7235

The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47

Samsung 

S3C7238/P7238/C7235/P7235

ELECTRICAL DATA

Table 14-6. A.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Instruction cycle

tCY

VDD = 2.7 V to 5.5 V

0.67

–

time (1)

VDD = 1.8 V to 4.5 V

0.95

–

With subsystem clock (fxt)

114

122

TCL0 input

fTI0

VDD = 2.7 V to 5.5 V

0

–

frequency

VDD = 1.8 V to 5.5V

TCL0 input high, tTIH0, tTIL0 VDD = 2.7 V to 5.5 V

0.48

–

low width

VDD = 1.8 V to 5.5 V

1.8

SCK cycle time

tKCY

VDD = 2.7 V to 5.5 V

External SCK source

800

–

Internal SCK source

650

VDD = 1.8 V to 5.5 V

External SCK source

3200

Internal SCK source

3800

SCK high, low

width

tKH, tKL

VDD = 1.8 V to 5.5 V

External SCK source

Internal SCK source

400

–

tKCY/2 – 50

VDD = 1.8 V to 5.5 V

External SCK source

1600

SI setup time to

Internal SCK source

tSIK

External SCK source

tKCY/2 – 150

100

–

SCK high

Internal SCK source

150

SI hold time to

tKSI

External SCK source

400

–

SCK high

Internal SCK source

400

Output delay for

SCK to SO

tKSO

VDD = 2.7 V to 5.5 V

External SCK source

–

–

Internal SCK source

VDD = 1.8 V to 5.5 V

External SCK source

Internal SCK source

Interrupt input

tINTH,

tINTL

INT0

(2)

–

high, low width

INT1, INT2, INT4, KS0–KS7

10

RESET Input Low

Width

tRSL Input

10

–

Max

Units

64

µs

64

125

1.5

MHz

1

MHz

–

µs

–

ns

–

ns

–

ns

–

ns

300

ns

250

1000

1000

–

µs

–

µs

NOTES:

1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.

2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.

14-7

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