PSD9342V10MIT Просмотр технического описания (PDF) - STMicroelectronics

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PSD9342V10MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

“Programming Flash Memory”, on page 19, for de-

tails.

Table 8. Status Bit

Functional Block

FS0-FS7/CSBOOT0-

CSBOOT3

DQ7

DQ6

DQ5 DQ4 DQ3 DQ2

DQ1

DQ0

Flash Memory

VIH

Data Toggle Error

Polling Flag Flag

X

Erase

Time-

out

X

X

X

Note: 1. X = Not guaranteed value, can be read either 1 or 0.

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.

3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

Data Polling Flag (DQ7). When erasing or pro-

gramming in Flash memory, the Data Polling Flag

(DQ7) bit outputs the complement of the bit being

entered for programming/writing on the DQ7 bit.

Once the Program instruction or the Write opera-

tion is completed, the true logic value is read on

the Data Polling Flag (DQ7) bit (in a Read opera-

tion).

s Data Polling is effective after the fourth Write

pulse (for a Program instruction) or after the

sixth Write pulse (for an Erase instruction). It

must be performed at the address being

programmed or at an address within the Flash

memory sector being erased.

s During an Erase cycle, the Data Polling Flag

(DQ7) bit outputs a 0. After completion of the

cycle, the Data Polling Flag (DQ7) bit outputs

the last bit programmed (it is a 1 after erasing).

s If the byte to be programmed is in a protected

Flash memory sector, the instruction is ignored.

s If all the Flash memory sectors to be erased are

protected, the Data Polling Flag (DQ7) bit is

reset to 0 for about 100 µs, and then returns to

the previous addressed byte. No erasure is

performed.

Toggle Flag (DQ6). The PSD offers another way

for determining when the Flash memory Program

cycle is completed. During the internal Write oper-

ation and when either the FS0-FS7 or CSBOOT0-

CSBOOT3 is true, the Toggle Flag (DQ6) bit tog-

gles from 0 to 1 and 1 to 0 on subsequent attempts

to read any byte of the memory.

When the internal cycle is complete, the toggling

stops and the data read on the Data Bus D0-D7 is

the addressed memory byte. The device is now

accessible for a new Read or Write operation. The

cycle is finished when two successive Reads yield

the same output data.

s The Toggle Flag (DQ6) bit is effective after the

fourth Write pulse (for a Program instruction) or

after the sixth Write pulse (for an Erase

instruction).

s If the byte to be programmed belongs to a

protected Flash memory sector, the instruction

is ignored.

s If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag (DQ6) bit

toggles to 0 for about 100 µs and then returns to

the previous addressed byte.

Error Flag (DQ5). During a normal Program or

Erase cycle, the Error Flag (DQ5) bit is to 0. This

bit is set to 1 when there is a failure during Flash

memory Byte Program, Sector Erase, or Bulk

Erase cycle.

In the case of Flash memory programming, the Er-

ror Flag (DQ5) bit indicates the attempt to program

a Flash memory bit from the programmed state, 0,

to the erased state, 1, which is not valid. The Error

Flag (DQ5) bit may also indicate a Time-out condi-

tion while attempting to program a byte.

In case of an error in a Flash memory Sector Erase

or Byte Program cycle, the Flash memory sector in

which the error occurred or to which the pro-

grammed byte belongs must no longer be used.

Other Flash memory sectors may still be used.

The Error Flag (DQ5) bit is reset after a Reset

Flash instruction.

Erase Time-out Flag (DQ3). The Erase Time-

out Flag (DQ3) bit reflects the time-out period al-

lowed between two consecutive Sector Erase in-

structions. The Erase Time-out Flag (DQ3) bit is

reset to 0 after a Sector Erase cycle for a time pe-

riod of 100 µs + 20% unless an additional Sector

Erase instruction is decoded. After this time peri-

od, or when the additional Sector Erase instruction

is decoded, the Erase Time-out Flag (DQ3) bit is

set to 1.

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