VE28F008-95 Просмотр технического описания (PDF) - Intel

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VE28F008-95

8 MBIT (1 MBIT x 8) FLASH MEMORY

Intel 

VE28F008

ALTERNATIVE CE-CONTROLLED WRITES(1)

Symbol

Parameter

Notes

VE28F008-95(6)

Min

Max

Unit

tAVAV

tWC

Write Cycle Time

95

tPHEL

tPS

RP High Recovery to CE Going Low

2

1

tWLEL

tWS

WE Setup to CE Going Low

0

tELEH

tCP

CE Pulse Width

50

tVPEH

tVPS VPP Setup to CE Going High

2

100

tAVEH

tAS

Address Setup to CE Going High

3

40

tDVEH

tDS

Data Setup to CE Going High

4

40

tEHDX

tDH

Data Hold from CE High

5

tEHAX

tAH

Address Hold from CE High

5

tEHWH

tWH

WE Hold from CE High

0

tEHEL

tEPH CE Pulse Width High

25

tEHRL

CE High to RY BY Going Low

tEHQV1

Duration of Byte Write Operation

5

6

tEHQV2

Duration of Block Erase Operation

5

03

tEHGL

Write Recovery before Read

0

tQVVL

tVPH VPP Hold from Valid SRD RY BY High

25

0

ns

ms

ns

ns

ns

ns

ns

ns

ns

ns

ns

100

ns

ms

sec

ms

ns

NOTES

1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE

defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be mea-

sured relative to the CE waveform

2 Sampled not 100% tested

3 Refer to Table 3 for valid AIN for byte write or block erasure

4 Refer to Table 3 for valid DIN for byte write or block erasure

5 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at

VPPH until determination of byte write block erase success (SR 3 4 5 e 0)

6 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics

23

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