M28F008 Просмотр технического описания (PDF) - Intel

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M28F008

8-Mbit (1Mbit x 8) flash memory

Intel 

M28F008

Power Supply Decoupling

Flash memory power switching characteristics re-

quire careful device decoupling System designers

are interested in 3 supply current issues standby

current levels (ISB) active current levels (ICC) and

transient peaks produced by falling and rising edges

of CE Transient current magnitudes depend on the

device outputs’ capacitive and inductive loading

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks

Each device should have a 0 1 mF ceramic capacitor

connected between each VCC and GND and be-

tween its VPP and GND These high frequency low

inherent-inductance capacitors should be placed as

close as possible to package leads Additionally for

every 8 devices a 4 7 mF electrolytic capacitor

should be placed at the array’s power supply con-

nection between VCC and GND The bulk capacitor

will overcome voltage slumps caused by PC board

trace inductances

VPP Trace on Printed Circuit Boards

Writing flash memories while they reside in the tar-

get system requires that the printed circuit board

designer pay attention to the VPP power supply

trace The VPP pin supplies the memory cell current

for writing and erasing Use similar trace widths and

layout considerations given to the VCC power bus

Adequate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots

VCC VPP RP Transitions and the

Command Status Registers

Byte write and block erase completion are not guar-

anteed if VPP drops below VPPH If the VPP Status bit

of the Status Register (SR 3) is set to ‘‘1’’ a Clear

Status Register command MUST be issued before

further byte write block erase attempts are allowed

by the WSM Otherwise the Byte Write (SR 4) or

Erase (SR 5) Status bits of the Status Register will

be set to ‘‘1’’s if error is detected RP transitions to

VIL during byte write and block erase also abort the

operations Data is partially altered in either case

and the command sequence must be repeated after

normal operation is restored Device poweroff or RP

transitions to VIL clear the Status Register to initial

value 10000 for the upper 5 bits

The Command User Interface latches commands as

issued by system software and is not altered by VPP

or CE transitions or WSM actions Its state upon

powerup after exit from deep powerdown or after

VCC transitions below VLKO is Read Array Mode

After byte write or block erase is complete even

after VPP transitions down to VPPL the Command

User Interface must be reset to Read Array mode via

the Read Array command if access to the memory

array is desired

Power Up Down Protection

The M28F008 is designed to offer protection against

accidental block erasure or byte writing during power

transitions Upon power-up the M28F008 is indiffer-

ent as to which power supply VPP or VCC powers

up first Power supply sequencing is not required

Internal circuitry in the M28F008 ensures that the

Command User Interface is reset to the Read Array

mode on power up

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is

active Since both WE and CE must be low for a

command write driving either to VIH will inhibit

writes The Command User Interface architecture

provides an added level of protection since altera-

tion of memory contents only occurs after success-

ful completion of the two-step command sequences

Finally the device is disabled until RP is brought to

VIH regardless of the state of its control inputs This

provides an additional level of memory protection

Power Dissipation

When designing portable systems designers must

consider battery power consumption not only during

device operation but also for data retention during

system idle time Flash nonvolatility increases us-

able battery life because the M28F008 does not

consume any power to retain code or data when the

system is off

In addition the M28F008’s deep powerdown mode

ensures low power dissipation even when system

power is applied For example portable PCs and

other power sensitive applications using an array of

M28F008s for solid-state storage can lower RP to

VIL in standby or sleep modes reducing power con-

sumption If access to the M28F008 is again need-

ed the part can again be read following the tPHQV

and tPHWL wakeup cycles required after RP is first

raised back to VIH See AC Characteristics Read-

Only and Write Operations and Figures 8 and 9 for

more information

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