DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
FIGURE 42- EGRESS INTERFACE TIMING - CLOCK MASTER: FULL DS1
MODE................................................................................................... 254
FIGURE 43- EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : NXDS0
MODE................................................................................................... 255
FIGURE 44- INGRESS INTERFACE TIMING - CLOCK SLAVE MODES ....... 256
FIGURE 45- INGRESS INTERFACE TIMING - CLOCK MASTER MODES.... 257
FIGURE 46- TRANSMIT LINE INTERFACE TIMING ...................................... 258
FIGURE 47- LINE INTERFACE INPUT TIMING.............................................. 259
FIGURE 48- JTAG PORT INTERFACE TIMING DIAGRAM ............................ 261
FIGURE 49- 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R
SUFFIX):............................................................................................... 264
FIGURE 50- 128 PIN CHIP ARRAY BALL GRID ARRAY (N SUFFIX):........... 265
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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