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PIC18F65J94 Просмотр технического описания (PDF) - Microchip Technology

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PIC18F65J94 Datasheet PDF : 696 Pages
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PIC18F97J94 FAMILY
FIGURE 1-1:
64-PIN DEVICE BLOCK DIAGRAM
Table Pointer<21>
inc/dec logic
21
20
Address Latch
Program Memory
Data Latch
8
Data Bus<8>
88
PCLATU PCLATH
PCU PCH PCL
Program Counter
31-Level Stack
STKPTR
Table Latch
Data Latch
Data Memory
(4 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
inc/dec
logic
ROM Latch
Instruction Bus <16>
IR
Address
Decode
OSC2/CLKO
OSC1/CLKI
Timing
Generation
INTRC
Oscillator
8 MHz
Oscillator
Precision
Band Gap
Reference
Voltage
Regulator
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
HLVD
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
8
ALU<8>
8
VDDCORE/VCAP VDD, VSS
MCLR
Timer0
Timer1
Timer
2/4/6/8
Timer
3/5
CTMU
A/D
LCD
Comparator
10/12-Bit 224 Pixels
1/2/3
PORTA
RA<7:0>(1,2)
PORTB
RB<7:0>(1)
PORTC
RC<7:0>(1)
PORTD
RD<7:0>(1)
PORTE
RE<7:0>(1)
PORTF
RF<7:2>(1)
PORTG
RG<4:0>(1)
CCP
4/5/6/7/8/9/10
ECCP
1/2/3
EUSART1 EUSART2 RTCC
MSSP1/2
USB
EUSART3 EUSART4
Note 1:
2:
See Table 1-4 for I/O port pin descriptions.
RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
DS30575A-page 14
2012 Microchip Technology Inc.

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