LF3338 Просмотр технического описания (PDF) - LOGIC Devices

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LF3338

8-Bit Vertical Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

LF3338

8-Bit Vertical Digital Image Filter

SIGNAL DEFINITIONS

Power

VCC and GND

+3.3 V power supply. All pins must be

connected.

FIGURE 2. INPUT FORMATS

Input Data

765

–27 26 25

(Sign)

210

22 21 20

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers.

Inputs

DIN7-0 — Data Input

DIN7-0 is the 8-bit registered data input

port. Data is latched on the rising edge

of CLK.

VB7-0 — Field Filtering Data Input

VB7-0 is the 8-bit registered data input

port used only when implementing

Odd and Even Field Filtering (see

Functional Description section for a full

discussion). Data is latched on the

rising edge of CLK.

CF11-0 — Coefficient Input

CF11-0 is used to load data into the

coefficient banks and configuration/

control registers. Data present on

CF11-0 is latched into the LF InterfaceTM

on the rising edge of CLK when LD is

LOW (see the LF InterfaceTM section for

a full discussion).

CA7-0 — Coefficient Address

CA7-0 determines which row of data in

the coefficient banks is fed to the

multipliers. CA7-0 is latched into the

Coefficient Address Register on the

rising edge of CLK when CEN is LOW.

Outputs

DOUT15-0 — Data Output

DOUT15-0 is the 16-bit registered data

output port.

TABLE 1. OUTPUT FORMATS

SLCT4-0 S15 S14 S13

···

00000 F15 F14 F13

···

00001 F16 F15 F14

···

00010 F17 F16 F15

···

·

···

·

···

·

···

01110 F29 F28 F27

···

01111 F30 F29 F28

···

10000 F31 F30 F29

···

COUT7-0 — Cascade Data Output

COUT7-0 is a 8-bit cascade output

port. COUT7-0 on one device

should be connected to DIN7-0 of

another LF3338.

Controls

LD — Coefficient Load

When LD is LOW, data on CF11-0

is latched into the LF InterfaceTM

on the rising edge of CLK. When

LD is HIGH, data can not be

latched into the LF InterfaceTM.

When enabling the LF InterfaceTM

for data input, a HIGH to LOW

transition of LD is required in

order for the input circuitry to

function properly. Therefore, LD

must be set HIGH immediately

after power up to ensure proper

operation of the input circuitry

(see the LF InterfaceTM section for

a full discussion).

Coefficient Data

11 10 9

–20 2–1 2–2

(Sign)

210

2–9 2–10 2–11

S8 S7

F8 F7

F9 F8

F10 F9

··

··

··

F22 F21

F23 F22

F24 F23

···

···

···

···

···

···

···

S2 S1 S0

F2 F1 F0

F3 F2 F1

F4 F3 F2

···

···

···

F16 F15 F14

F17 F16 F15

F18 F17 F16

FIGURE 3. ACCUMULATOR FORMAT

Accumulator Output

31 30 29

–216 215 214

(Sign)

210

2–13 2–14 2–15

PAUSE — LF InterfaceTM Pause

When PAUSE is HIGH, the LF

InterfaceTM loading sequence is halted

until PAUSE is returned to a LOW

state. This effectively allows the user

to load coefficients and control

registers at a slower rate than the

master clock (see the LF InterfaceTM

section for a full discussion).

CEN — Coefficient Address Enable

When CEN is LOW, data on CA7-0 is

latched into the Coefficient Address

Register on the rising edge of CLK.

When CEN is HIGH, data on CA7-0 is

not latched and the register’s contents

will not be changed.

Video Imaging Products

3

04/06/1999–LDS.3338-B

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