PEB2055 Просмотр технического описания (PDF) - Siemens AG
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PEB2055 Datasheet PDF : 269 Pages
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PEB 2055
PEF 2055
Overview
1.3 Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I) Function
EPIC-S EPIC
Output (O)
17 17 PDC I
PCM Interface Data Clock
Single or double data rate.
6
6
RxD0 I
5
5
RxD1 I
4
4
RxD2 I
3
3
RxD3 I
Receive PCM Interface Data
Time-slot oriented data is received on this pins
and forwarded into the downstream data memory
of the EPIC.
9
9
TxD0 O
11 11 TxD1 O
13 13 TxD2 O
15 15 TxD3 O
Transmit PCM Interface Data
Time slot oriented data is shifted out of the
EPIC’s upstream data memory on this lines. For
time-slots which are flagged in the tristate
data memory or when bit OMDR:PSB is reset
the pins are set to high impedance state.
8
8
TSC0 O
10 10 TSC1 O
12 12 TSC2 O
14 14 TSC3 O
Tristate Control
Supplies a control signal for an external driver.
These lines are “low” when the corresponding
TxD outputs are valid. During reset these lines
are “high”.
34 34 FSC I/O
Frame Synchronization
Input or output in IOM configuration. Direction
indication signal in SLD mode.
33 33 DCL I/O
Data Clock
Input or output in IOM, slave clock in SLD
configuration. In IOM configuration single or
double data rate, single data rate in SLD mode.
38 38 DU0/SIP4 I/IO (OD) Data Upstream Input; IOM or PCM configuration.
37 37 DU1/SIP5 I/IO (OD) Serial Interface Port, SLD configuration.
-
36 * DU2/SIP6 I/IO (OD) Depending on the bit OMDR:COS these lines
-
35 * DU3/SIP7 I/IO (OD) have push pull or open drain characteristic.
For unassigned channels or when bit
OMDR:CSB is reset the pins are in the state
high impedance.
* Note: EPIC-1 only
Semiconductor Group
12
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