Q67100-H8322 Просмотр технического описания (PDF) - Siemens AG

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производитель

Q67100-H8322

Memory Time Switch CMOS (MTSC)

Siemens AG 

PEB 2045

PEF 2045

1.1 Pin Definitions and Functions

Pin No.

P-LCC

1

3

4

7

9

11

13

14

15

16

17

18

19

5

8

10

12

20

21

22

23

24

Pin No.

P-DIP

1

2

3

5

7

9

11

12

13

14

15

16

17

4

6

8

10

18

19

20

21

22

Symbol

VSS

SP

IN1

IN5

IN9

IN13

IN14

IN15

IN10

IN11

IN6

IN7

IN2

IN0/TSC0

IN4/TSC1

IN8/TSC2

IN12/TSC3

IN3/DCL

A0

CS

VDD

RD

Input (I) Function

Output (O)

I

Ground (OV)

I

Synchronization Pulse: The PEx 2045 is

synchronized relative to the PCM system via

this line.

I

PCM-Input Ports: Serial data is received at

I

these lines at standard TTL levels.

I

I

I

I

I

I

I

I

I

I/O

PCM-Input Port / Tristate Control: In standard

I/O

configuration these pins are used as input lines,

I/O

in primary access configuration they supply

I/O

control signals for external devices.

I/O

PCM-Input Port / Data Clock: In standard

configuration IN3 is the PCM input line 3, in

primary access configuration it provides a

2048-kHz data clock for the synchronous

interface.

I

Address 0: When high, the indirect register

access mechanism is enabled. If A0 is logical 0

the mode and status registers can be written to

and read respectively.

I

Chip Select: A low level selects the PEx 2045

for a register access operation.

I

Supply voltage: 5 V ± 5 %.

I

Read: This signal indicates a read operation

and is internally sampled only if CS is active.

The MTSC puts data from the selected internal

register on the data bus with the falling edge of

RD. RD is active low.

Semiconductor Group

3

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