HT48R06A-1(2000) Просмотр технического описания (PDF) - Holtek Semiconductor

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HT48R06A-1
(Rev.:2000)

8-Bit OTP Microcontroller

Holtek Semiconductor 

Preliminary

HT48R06A-1

put/output latches can be set or cleared by "SET

[m].i" and "CLR [m].i" (m=12H, 14H or 16H) in-

structions.

Some instructions first input data and then fol-

low the output operations. For example, "SET

[m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read

the entire port states into the CPU, execute the

defined operations (bit-operation), and then

write the results back to the latches or the accu-

mulator.

Each line of port A has the capability of wak-

ing-up the device. The highest 6-bit of port C and

5 bits of port B are not physically implemented;

on reading them a "0" is returned whereas writ-

ing then results in a no-operation. See Applica-

tion note.

There is a pull-high option available for all I/O

lines. Once the pull-high option is selected, all

I/O lines have pull-high resistors. Otherwise,

the pull-high resistors are absent. It should be

noted that a non-pull-high I/O line operating in

input mode will cause a floating state.

The PB0 and PB1 are pin-shared with BZ and

BZ signal, respectively. If the BZ/BZ option is

selected, the output signal in output mode of

PB0/PB1 will be the PFD signal generated by

timer/event counter overflow signal. The input

mode always remaining its original functions.

Once the BZ/BZ option is selected, the buzzer

output signals are controlled by PB0 data regis-

ter only. The I/O functions of PB0/PB1 are

shown below.

PB0 I/O

I I I I O OOO O O

PB1 I/O

I OOO I I IOOO

PB0/PB1 Mode x C B B C B B C B B

PB0 Data

x x 0 1 D 0 1 D0 0 1

PB1 Data

x D x x x x x D1 x x

PB0 Pad Status I I I I D 0 B D0 0 B

PB1 Pad Status I D 0 B I I I D1 0 B

Note: I: input; O: output; D, D0, D1: data;

B: buzzer option, BZ or BZ; x: don't care

C: CMOS output

V DD

D a ta B u s

C o n tr o l B it

PU

DQ

W r ite C o n tr o l R e g is te r

C h ip R e s e t

R e a d C o n tr o l R e g is te r

CK QB

S

D a ta B it

DQ

P A 0~P A 7

P B 0~P B 2

P C 0~P C 1

W r ite D a ta R e g is te r

(P B 0 , P B 1

O n ly )

PB0

EXT

R e a d D a ta R e g is te r

S y s te m W a k e -u p

( P A o n ly )

IN T fo r P C 0 O n ly

T M R fo r P C 1 O n ly

CK QB

S

M

U

X

M

U

X

EXTEN

( P B 0 , P B 1 O n ly )

O P 0~O P 7

E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r

Input/output ports

18

February 25, 2000

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