HT48R06A-1(2000) Просмотр технического описания (PDF) - Holtek Semiconductor
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HT48R06A-1 Datasheet PDF : 44 Pages
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Preliminary
HT48R06A-1
Timer/event counter
A timer/event counter (TMR) is implemented in
the microcontroller. The timer/event counter
contains an 8-bit programmable count-up coun-
ter and the clock may come from an external
source or the system clock.
Using the internal system clock, there is only
one reference time-base. The internal clock
source comes from fSYS. The external clock in-
put allows the user to count external events,
measure time intervals or pulse widths, or to
generate an accurate time base.
There are 2 registers related to the timer/event
counter; TMR ([0DH]), TMRC ([0EH]). Two phys-
ical registers are mapped to TMR location; writ-
ing TMR makes the starting value be placed in
the timer/event counter preload register and
reading TMR gets the contents of the timer/event
counter. The TMRC is a timer/event counter con-
trol register, which defines some options.
Label (TMRC) Bits
Function
PSC0~PSC2
TE
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
010: fINT=fSYS/8
0~2 011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
3
To define the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
¾
5 Unused bits, read as"0"
TM0
TM1
To define the operating mode
6
7
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC register
fS Y S
8 - s ta g e p r e s c a le r
fIN T
8 -1 M U X
TM 1
TM 0
P S C 2~P S C 0 TM R
TE
D a ta B u s
T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
TM 1
P u ls e W id th
M e a s u re m e n t
TM 0
M o d e C o n tro l
TO N
T im e r /e v e n t
C o u n te r
O v e r flo w
to In te rru p t
1 /2
BZ
BZ
Timer/event counter
16
February 25, 2000
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