HT48R06A-1(2000) Просмотр технического описания (PDF) - Holtek Semiconductor

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HT48R06A-1
(Rev.:2000)

8-Bit OTP Microcontroller

Holtek Semiconductor 

Preliminary

HT48R06A-1

next instruction execution, this will be executed

immediately after the dummy period is fin-

ished.

To minimize power consumption, all the I/O

pins should be carefully managed before enter-

ing the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different

from other chip reset conditions, since it can

perform a "warm reset" that resets only the PC

and SP, leaving the other circuits in their origi-

nal state. Some registers remain unchanged

during other reset conditions. Most registers

are reset to the ²initial condition² when the re-

set conditions are met. By examining the PD

and TO flags, the program can distinguish be-

tween different "chip resets".

TO PD

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1

u

WDT time-out during normal opera-

tion

1 1 WDT wake-up HALT

Note: "u" means "unchanged"

To guarantee that the system oscillator is

started and stabilized, the SST (System

Start-up Timer) provides an extra-delay of 1024

system clock pulses when the system reset

(power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is

added during the reset period. Any wake-up

from HALT will enable the SST delay.

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset timing chart

V DD

RES

Reset circuit

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset configuration

The functional unit chip reset status are shown

below.

PC

000H

Interrupt Disable

Prescaler Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/event

Counter

Off

Input/output

Ports

Input

mode

SP

Points to the top of

the stack

14

February 25, 2000

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