AT89LV52 Просмотр технического описания (PDF) - Atmel Corporation
Номер в каталоге
Компоненты Описание
производитель
AT89LV52 Datasheet PDF : 22 Pages
| |||
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 2.7V to 6.0V and Load Capacitance = 80 pF.
Symbol Parameter
12 MHz Osc
Variable Oscillator
Min
Max
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
tQVXH
Output Data Setup to Clock Rising Edge
700
tXHQX
Output Data Hold After Clock Rising Edge
50
tXHDX
Input Data Hold After Clock Rising Edge
0
tXHDV
Clock Rising Edge to Input Data Valid
12tCLCL
10tCLCL-133
2tCLCL-117
0
700
10tCLCL-133
Shift Register Mode Timing Waveforms
Units
µs
ns
ns
ns
ns
AC Testing Input/Output Waveforms (1) Float Waveforms (1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for
a logic 1 and 0.45V for a logic 0. Timing measure-
ments are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
4-102
Not
Share Link: 