PCF8577CT/3,118 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF8577CT/3,118 Datasheet PDF : 33 Pages
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NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
6.2 Pin description
Table 4. Pin description
Symbol
Pin
Type
S32 to S1
1 to 32 outputs
BP1
33
input/output
A2/BP2
34
input/output
VDD
A1
A0/OSC
VSS
SCL
SDA
35
supply
36
input
37
input
38
supply
39
input
40
input/output
Description
segment outputs
cascaded sync input/backplane output
hardware address line and cascade sync
input/backplane output
supply voltage
hardware address line input
hardware address line and oscillator pin input
ground supply
I2C-bus clock line input
I2C-bus data line input/output
7. Functional description
7.1 Hardware subaddress lines A0, A1, and A2
The hardware subaddress lines A0, A1, and A2 are used to program the device
subaddress for each PCF8577C connected to the I2C-bus. Lines A0 and A2 are shared
with OSC and BP2 respectively to reduce pinout requirements.
1. Line A0 is defined as LOW (logic 0) when this pin is used for the local oscillator or
when connected to VSS. Line A0 is defined as HIGH (logic 1) when connected to VDD.
2. Line A1 must be defined as LOW (logic 0) or as HIGH (logic 1) by connection to VSS
or VDD respectively.
3. In the direct drive mode, the second backplane signal BP2 is not used and the
A2/BP2 pin is exclusively the A2 input. Line A2 is defined as LOW (logic 0) when
connected to VSS or, if this is not possible, by leaving it unconnected (internal
pull-down). Line A2 is defined as HIGH (logic 1) when connected to VDD.
4. In the duplex drive mode, the second backplane signal BP2 is required and the
A2 signal is undefined. In this mode, device selection is made exclusively from
lines A0 and A1.
7.2 Oscillator A0/OSC
The PCF8577C has a single-pin built-in oscillator which provides the modulation for the
LCD segment driver outputs. One external resistor and one external capacitor are
connected to the A0/OSC pin to form the oscillator (see Figure 13 and Figure 14). For
correct start-up of the oscillator after power-on, the resistor and capacitor must be
connected to the same VSS/VDD as the chip. In an expanded system containing more than
one PCF8577C the backplane signals are usually common to all devices and only one
oscillator is required. The devices which are not used for the oscillator are put into the
cascade mode by connecting the A0/OSC pin to either VDD or VSS depending on the
required state for A0. In the cascade mode, each PCF8577C is synchronized from the
backplane signals.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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