PCF2119VU/2/F2 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF2119VU/2/F2 Datasheet PDF : 79 Pages
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NXP Semiconductors
PCF2119x
LCD controllers/drivers
10.2.1 Basic instructions (bit H = 0 or 1)
10.2.1.1 Function_set
Table 12. Function_set bit description
Bit
Symbol
Value
Description
RS
-
0
see Table 10
R/W -
0
7 to 5 -
001
fixed value
4
DL
interface data length (for parallel mode only)
0
[1] 2 × 4 bits (DB7 to DB4)
1
[2] 8 bits (DB7 to DB0)
3
-
0
unused
2
M
[3] number of display lines
0
1 line × 32 characters
1
[4] 2 line × 16 characters
1
SL
multiplex mode
0
1:18 multiplex drive mode, 1 × 32 or 2 × 16
character display
1
[4][5] 1:9 multiplex drive mode, 1 × 16 character display
0
H
instruction set control
0
basic instruction set plus standard instruction set
1
[4] basic instruction set plus extended instruction set
[1] When 4-bit width is selected, data is transmitted in two cycles using the parallel-bus. In a 4-bit application
ports DB3 to DB0 should be left open-circuit (internal pull-ups).
[2] Default value after power-on in I2C-bus mode.
[3] No impact if SL = 1.
[4] Due to the internal pull-ups on DB3 to DB0 in a 4-bit application, the first Function_set after power-on sets
bits M, SL and H to logic 1. A second Function_set must be sent to set bits M, SL and H to the required
values.
[5] Independent of bit M and bit L of the Screen_conf instruction (see Section 10.2.3.1). Only row 1 to row 8
and row 17 are used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2 × 16
character display mode, however, the second line cannot be displayed.
10.2.1.2 BF_AC instructions
Table 13. BF_AC bit
Bit
Symbol
RS
-
R/W -
7
BF
Value
0
1
0
1
6 to 0 AC
0000000 to
111 1111
Description
see Table 10
[1] read busy flag
next instruction will be executed
internal operation is in progress;
next instruction will not be executed until BF = 0
read address counter
[1] It is recommended that the BF status is checked before the next write operation is started.
PCF2119X_5
Product data sheet
Rev. 05 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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