PCA9525D Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9525D Datasheet PDF : 22 Pages
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NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9525
Simple 2-wire bus buffer
EN 1
SCL_OUT 2
SCL_IN 3
VSS 4
8 VDD
7 SDA_OUT
PCA9525D
6 SDA_IN
5 DIR
002aaf330
Fig 2. Pin configuration for SO8
EN 1
SCL_OUT 2
SCL_IN 3
VSS 4
PCA9525DP
8 VDD
7 SDA_OUT
6 SDA_IN
5 DIR
002aaf331
Fig 3. Pin configuration for TSSOP8
6.2 Pin description
Table 2. Pin description
Symbol
Pin
EN
1
SCL_OUT
2
SCL_IN
3
VSS
4
DIR
5
SDA_IN
6
SDA_OUT
7
VDD
8
Description
enable
clock buffer, slave side
clock buffer, master side
supply ground
clock direction
data buffer, master side
data buffer, slave side
positive supply
7. Functional description
Refer to Figure 1 “Block diagram of PCA9525”.
7.1 VDD, VSS — supply pins
The power supply voltage for the PCA9525 may be any voltage in the range 2.7 V to
5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports
is a percentage of the IC’s power supply, hence noise margin considerations should be
taken into account when selecting an operating voltage.
7.2 SCL_IN, SCL_OUT — clock signal inputs/outputs
The clock signal buffer is unidirectional, although the direction may be reversed under
control of the direction pin (DIR). In normal bus operations, for example the I2C-bus, the
master device generates a unidirectional clock signal to the slave. For lowest cost, the
PCA9525 combines unidirectional buffering of the clock signal with a bidirectional buffer
for the data signal. Clock stretching is therefore not supported and slave devices that may
require clock stretching must be accommodated by the master adopting an appropriate
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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