PCA9513A Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9513A Datasheet PDF : 26 Pages
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NXP Semiconductors
7. Pinning information
7.1 Pinning
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
ENABLE 1
8 VCC
SCLOUT 2 PCA9513AD 7 SDAOUT
SCLIN 3 PCA9514AD 6 SDAIN
GND 4
5 READY
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Fig 3. Pin configuration for SO8
ENABLE 1
SCLOUT 2
SCLIN 3
GND 4
PCA9513ADP
PCA9514ADP
8 VCC
7 SDAOUT
6 SDAIN
5 READY
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Fig 4. Pin configuration for TSSOP8
(MSOP8)
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
ENABLE 1
Chip enable. Grounding this input puts the part in a Low current (< 1 µA)
mode. It also disables the rise time accelerators, isolates SDAIN from
SDAOUT and isolates SCLIN from SCLOUT.
SCLOUT 2
serial clock output to and from the SCL bus on the card
SCLIN
3
serial clock input to and from the SCL bus on the backplane
GND
4
Ground. Connect this pin to a ground plane for best results.
READY
5
open-drain output which pulls LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT, and goes HIGH when the two
sides are connected
SDAIN
6
serial data input to and from the SDA bus on the backplane
SDAOUT 7
serial data output to and from the SDA bus on the card
VCC
8
power supply
8. Functional description
Refer to Figure 1 “Block diagram of PCA9513A” and Figure 2 “Block diagram of
PCA9514A”.
8.1 Start-up
An undervoltage and initialization circuit holds the parts in a disconnected state which
presents high-impedance to all SDAn and SCLn pins during power-up. A LOW on the
ENABLE pin also forces the parts into the low current disconnected state when the ICC is
essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is
powered and the ENABLE is taken from LOW to HIGH it enters an initialization state
where the internal references are stabilized and the 92 µA input pull-ups (on the
PCA9513A) is enabled. At the end of the initialization state the ‘Stop Bit And Bus Idle’
detect circuit is enabled. With the ENABLE pin HIGH long enough to complete the
initialization state (ten) and remaining HIGH when all the SDAn and SCLn pins have been
PCA9513A_PCA9514A_4
Product data sheet
Rev. 04 — 18 August 2009
© NXP B.V. 2009. All rights reserved.
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