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PCA9512BD

Level shifting hot swappable I2C-bus and SMBus bus buffer

NXP Semiconductors. 

NXP Semiconductors

PCA9512A; PCA9512B

Level shifting hot swappable I2C-bus and SMBus bus buffer

8.9 Voltage level translator discussion

8.9.1 Summary

There are two popular configurations for the interface of low voltage logic (i.e., core

processor with 3.3 V supply) to standard bus levels (i.e., I2C-bus with 5 V supply). A single

FET transistor and two additional resistors may be used effectively, or an

application-specific IC part requiring no external components and no additional resistors.

The FET solution becomes problematic as the low voltage logic levels trend downwards.

The FET solution will stop working completely when the FET specification is no longer

matched to the LOW level logic supply voltage requirements.

The dominant advantage of the FET solution is cost, but the IC part provides additional

advantages to the design, which increases reliability to the end user.

8.9.2 Why do level translation?

Advances in processing technology require lower supply voltages, due to reduced

clearances in the fabrication technology. Lower supply voltages drive down signal swings,

or require that on die high voltage I/O sections are added, creating larger die area, or

greater I/O pin count. Existing standards for interoperability of equipment connected by

cables or between subsystems require higher voltage signal swings (typically 5 V).

An external voltage level translator solves these problems, but requires additional parts.

8.10 Limitations of the FET voltage level translator

8.10.1

VGSth, gate-source threshold voltage

When the VA input is logic LOW, the FET is turned on, pulling VB output LOW. This can

only occur when the threshold voltage of the FET is less than the VA supply voltage minus

the maximum level of the VA signal, VAIL. Using CMOS logic thresholds of 0.3 and

0.7 times the supply, and a 1.1 V VA gives a worst-case of just 330 mV, much less than

VGSth of the popular 2N7002 FET.

VGSth; ID = 250 A; VDS = VGS; 1.1 V (min.)/1.6 V (typ.)/2.1 V (max.)

Additionally, the FET threshold voltage is specified in the linear region of the FET, with

weak conduction. Ideally the FET should have very low ON-resistance. For the 2N7002,

this is specified at 5 V VGS (not the 1 V available in this application). Note that the

ON-resistance decreases rapidly as VGS is increased beyond the VGSth specification.

Unintended operation in the linear region further compromises logic level noise immunity.

8.10.2 FET body diode voltage

The FET is required to conduct in both directions, as the I2C-bus is bidirectional. When

the VB input is logic LOW, the body diode of the FET conducts first, pulling the FET

source LOW along with the FET drain, until the FET conducts. During this transition the

forward voltage drop of the body diode reduces the available FET gain to source bias. The

body diode is specified:

VSD, source-drain voltage; IS = 115 mA; VGS = 0 V; 0.47 V (min.)/0.75 V (typ.)/1.1 V

(max.)

PCA9512A_PCA9512B

Product data sheet

Conduction of the FET body diode impacts both the delay time and logic transition speed.

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 1 March 2013

© NXP B.V. 2013. All rights reserved.

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