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PCA9511D

Hot swappable I2C-bus and SMBus bus buffer

NXP Semiconductors. 

Philips Semiconductors

Hot swappable I2C-bus and SMBus bus buffer

Product data sheet

PCA9511

Propagation delays

The delay for a rising edge is determined by the combined pull-up

current from the bus resistors and the rise time accelerator current

source and the effective capacitance on the lines. If the pull-up

currents are the same, any difference in rise time is directly

proportional to the difference in capacitance between the two sides.

The tPLH may be negative if the output capacitance is less than the

input capacitance and would be positive if the output capacitance is

larger than the input capacitance, when the currents are the same.

The tPHL can never be negative because the output does not start to

fall until the input is below 0.7VCC, and the output turn on has a

non-zero delay, and the output has a limited maximum slew rate,

and even if the input slew rate is slow enough that the output

catches up it will still lag the falling voltage of the input by the offset

voltage. The maximum tPHL occurs when the input is driven LOW

with zero delay and the output is still limited by its turn on delay and

the falling edge slew rate. The output falling edge slew rate is a

function of the internal maximum slew rate which is a function of

temperature. VCC and process, as well as the load current and the

load capacitance.

Rise time accelerators

During positive bus transitions a 2 mA current source is switched on

to quickly slew the SDA and SCL lines HIGH once the input level of

0.6 V is exceeded. The rising edge rate should be at least 1.25 V/µs

to guarantee turn on of the accelerators.

READY digital output

This pin provides a digital flag which is LOW when either ENABLE is

LOW or the start-up sequence described earlier in this section has

not been completed. READY goes HIGH when ENABLE is HIGH

and start-up is complete. The pin is driven by an open-drain

pull-down capable of sinking 3 mA while holding 0.4 V on the pin.

Connect a resistor of 10 kΩ to VCC to provide the pull-up.

ENABLE low current disable

Grounding the ENABLE pin disconnects the backplane side from the

card side, disables the rise-time accelerators, drives READY LOW,

disables the bus precharge circuitry, and puts the part in a low

current state. When the pin voltage is driven all the way to VCC, the

part waits for data transactions on both the backplane and card

sides to be complete before reconnecting the two sides.

Resistor pull-up value selection

The system pull-up resistors must be strong enough to provide a

positive slew rate of 1.25 V/µs on the SDA and SCL pins, in order to

activate the boost pull-up currents during rising edges. Choose

maximum resistor value using the formula:

R v 800 @ 103

VCC(MIN) * 0.6

C

where R is the pull-up resistor value in Ω, VCC(MIN) is the

minimum VCC voltage in volts and C is the equivalent bus

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always choose

R ≤ 16 kΩ for VCC = 5.5 V maximum, R ≤ 24 kΩ for VCC = 3.6 V

maximum. The start-up circuitry requires logic HIGH voltages on

SDAOUT and SCLOUT to connect the backplane to the card, and

these pull-up values are needed to overcome the precharge voltage.

See the curves in Figures 5 and 6 for guidance in resistor pull-up

selection.

30

RPU

(kΩ)

25

20

RMAX = 24 kΩ

15

RISE-TIME > 300 ns

21

RECOMMENDED

PULL-UP

5

0

0

100

200

300

400

Cb (pF)

SW02115

Figure 5. Bus requirements for 3.3 V systems

20

RPU

(kΩ)

15

21

5

RMAX = 16 kΩ

RISE-TIME

> 300 ns

RECOMMENDED

PULL-UP

0

0

100

200

300

400

Cb (pF)

SW02116

Figure 6. Bus requirements for 5 V systems

Minimum SDA and SCL capacitance requirements

The device connection circuitry requires a minimum capacitance

loading on the SDA and SCL pins in order to function properly. The

value of this capacitance is a function of VCC and the bus pull-up

resistance. Estimate the bus capacitance on both the backplane and

the card data and clock buses, and refer to Figures 5 and 6 to

choose appropriate pull-up resistor values. Note from the figures

that 5 V systems should have at least 47 pF capacitance on their

buses and 3.3 V systems should have at least 22 pF capacitance for

proper operation. Although the device has been designed to be

marginally stable with smaller capacitance loads, for applications

with less capacitance, provisions need to be made to add a

capacitor to ground to ensure these minimum capacitance

conditions if oscillations are noticed during initial signal integrity

verification.

2006 Aug 23

6

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