PC85132/232-1 Просмотр технического описания (PDF) - NXP Semiconductors.

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PC85132/232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCA85132

LCD driver for low multiplex rates

MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

SLAVE

RECEIVER

Fig 19. System configuration

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

mga807

8.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 20.

data output

by transmitter

data output

by receiver

SCL from

master

S

1

2

START

condition

Fig 20. Acknowledgement on the I2C-bus

not acknowledge

acknowledge

8

9

clock pulse for

acknowledgement

mbc602

PCA85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 April 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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