PCA9502 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9502 Datasheet PDF : 25 Pages
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NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Table 15. Static characteristics …continued
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
VDD = 2.5 V
Min
Max
I2C-bus inputs SCL, CS/A0, SI/A1
VIH
HIGH-level input voltage
1.6
5.5[1]
VIL
LOW-level input voltage
IL
leakage current
input; VI = 0 V or 5.5 V[1]
-
0.6
-
10
Ci
input capacitance
-
7
VDD = 3.3 V Unit
Min
Max
2.0
5.5[1] V
-
0.8 V
-
10 µA
-
7 pF
[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
13. Dynamic characteristics
Table 16. I2C-bus timing specifications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C; refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, except SDA output load = 400 pF.[1]
Symbol Parameter
Conditions
Standard-mode Fast-mode Unit
I2C-bus
I2C-bus
Min Max Min Max
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and
START condition
[2]
0
100
0 400 kHz
4.7
-
1.3
- µs
tHD;STA
tSU;STA
hold time (repeated) START condition
set-up time for a repeated START
condition
4.0
-
0.6
- µs
4.7
-
0.6
- µs
tSU;STO set-up time for STOP condition
4.7
-
0.6
- µs
tHD;DAT data hold time
tVD;ACK data valid acknowledge time
0
-
0
- ns
-
0.6
-
0.6 µs
tVD;DAT data valid time
SCL LOW to data out valid
-
0.6
-
0.6 ns
tSU;DAT
tLOW
tHIGH
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
250
-
150 - ns
4.7
-
1.3
- µs
4.0
-
0.6
- µs
tf
fall time of both SDA and SCL signals
-
300
- 300 ns
tr
rise time of both SDA and SCL signals
-
1000 -
300 ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50 ns
td1
I2C-bus GPIO output valid time
td4
I2C input pin interrupt valid time
td5
I2C input pin interrupt clear time
0.5
-
0.5
- µs
0.2
-
0.2
- µs
0.2
-
0.2
- µs
[1] A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to use it”. This brochure
may be ordered using the code 9398 393 40011.
[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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