PCA8565 Просмотр технического описания (PDF) - Philips Electronics
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PCA8565 Datasheet PDF : 26 Pages
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Philips Semiconductors
PCA8565
Real time clock/calender
For accurate read back of the countdown value, the I2C-bus clock (SCL) must be
operating at a frequency of at least twice the selected timer clock.
Table 24: Timer control (address 0EH) bits description
Bit
Symbol Value
Description
7
TE
0
timer is disabled
1
timer is enabled
1 to 0
TD1 and
TD0
timer source clock frequency select; these bits determine the source clock for the
countdown timer, see Table 25; when not in use, TD1 and TD0 should be set to
1⁄16 Hz for power saving
Table 25: TD1 and TD0: Timer frequency selection
TD1
TD0
TIMER Source clock frequency
0
0
4096 Hz
0
1
64 Hz
1
0
1 Hz
1
1
1⁄60 Hz
Table 26: Timer (address 0FH) bits description
Bit
Symbol Value
Description
7 to 0
timer
00 to FF
countdown value = n; CountdownPeriod = S----o---u----r--c---e---C-----l--o---c-n--k---F----r---e---q---u---e---n----c---y-
9397 750 10695
Product data
8.7 EXT_CLK test mode
A test mode is available which allows for on-board testing. In such a mode it is
possible to set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in control/status1 register. Then
pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal
with the signal applied to pin CLKOUT. Every 64 positive edges applied to
pin CLKOUT will then generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and
a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT,
is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be
set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is
reset to 0 (STOP must be cleared before the pre-scaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second
increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz
clock. When entering the test mode, no assumption as to the state of the pre-scaler
can be made.
Operation example:
1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1)
2. Set STOP (control/status 1, bit STOP = 1)
Rev. 01 — 31 March 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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