PCA5010H/F1 Просмотр технического описания (PDF) - Philips Electronics

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PCA5010H/F1

Pager baseband controller

Philips Electronics 

Philips Semiconductors

Pager baseband controller

Product specification

PCA5010

5 PINNING INFORMATION

SYMBOL

P3.4 and P3.5

AT

P2.0 to P2.7

P0.0 to P0.4

VDDA

AFCOUT

I(D1)

Q(D0)

VSSA

P0.5 to P0.7

P1.0 to P1.2

P1.3

PIN

1 and 2

3

4 to 11

12 to 16

17

18

19

20

21

22 to 24

25 to 27

28

TYPE

DESCRIPTION

I/O Port 3: P3.4 and P3.5 are configured as push-pull outputs only (Option 3R, see

Section 6.6). Using the software input commands or the secondary port

function is possible by driving the Port 3 output lines accordingly:

P3.4 secondary function: T0 (counter input for T0)

P3.5 secondary function: T1 (counter input for T1)

O Beeper high volume control output. Used to drive external bipolar transistor.

I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups (option 1S,

see Section 6.6.3). As inputs, Port 2 pins that are externally pulled LOW will

source current because of the internal pull-ups. (See Chapter 10: Ipu). Port 2

emits the high-order address byte during fetches from external program

memory. In this application, it uses strong internal pull-ups when emitting

logic 1s. Port 2 is also used to control the parallel programming mode of the

on-chip OTP.

I/O Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1S, see

Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by

the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed

low-order address and data bus during access to external program and data

memory. In this application, it uses strong internal pull-ups when emitting

logic 1s. Port 0 also outputs the code bytes during OTP programming

verification.

S supply voltage for the analog parts of the PCA5010 and the

receiver/synthesizer control signals (Port 0 pins)

O Buffered analog output of DAC for automatic receiver frequency control.

A voltage proportional to the offset of the receiver frequency can be generated.

Can be enabled/disabled by software.

I Input from receiver: may be demodulated NRZ signal or Zero-IF. In phase

limited signal.

I Input from receiver: may be demodulated NRZ signal or Zero-IF. Quadrature

limited signal.

S ground signal reference (for the analog parts) (connected to substrate)

I/O Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1R, 1R,

1S, see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled

HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the

multiplexed low-order address and data bus during access to external program

and data memory. In this application, it uses strong internal pull-ups when

emitting logic 1s. Port 0 also outputs the code bytes during OTP programming

verification.

I/O Port 1: Port 1 is an 8-bit quasi bidirectional I/O port with internal pull-ups.

Port 1 pins that have logic 1s written to them are pulled HIGH by the internal

pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally

pulled LOW will source current because of the internal pull-ups. (See

Chapter 10: Ipu). P1.0 to P1.2 have external interrupts INT2 (X3) to INT4 (X5)

assigned.

I/O If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.3 can be used as

general purpose P1 port pin. If the UART function is required, then a logic 1

must be written to P1.3. This I/O then becomes the RXD/data line of the UART.

1998 Nov 02

6

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