PC8240 Просмотр технического описания (PDF) - Atmel Corporation
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PC8240 Datasheet PDF : 42 Pages
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Table 14. PC8240 Maximum Two-wire Interface Input Frequency (Continued)
Max Two-wire Interface Input Frequency(1)
FDR Hex(2)
Divider (Dec)(2)
SDRAM_CLK SDRAM_CLK SDRAM_CLK SDRAM_CLK
at 25 MHz
at 33 MHz
at 50 MHz
at 100 MHz
14, 15
9216, 10240
16
21
32
64
16, 17, 3A, 3B, 3C, 3D
12288, 14336, 15360,
12
16
24
48
16384, 20480, 24576
18, 19
18432, 20480
8
10
16
32
1A, 1B, 3E, 3F
24576, 28672, 30720,
6
32768
8
12
24
1C, 1D
36864, 40960
4
5
8
16
Notes:
1E, 1F
49152, 61440
3
4
6
12
1. Values are in kHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique
output frequency as shown in Table 15 on page 26.
Table 15 provides the two-wire interface output AC timing specifications for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Table 15. Two-wire Interface Output AC Timing Specifications
Num
1
Characteristics
Start condition hold time
2
Clock low period
3
SCL/SDA rise time (from 0.5V to 2.4V)
4
Data hold time
5
SCL/SDA fall time (from 2.4V to 0.5V)
6
Clock high time
7
Data setup time (PC8240 as a master only)
8
Start condition setup time (for repeated start
condition only)
9
Stop condition setup time
Min
(FDR[5] == 0) x (DFDR/16)/2N +
(FDR[5] == 1) x (DFDR/16)/2M
DFDR/2
–
8.0 + (16 x 2FDR[4:2]) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
DFDR/2
(DFDR/2) - (Output data hold time)
DFDR + (Output start condition hold
time)
4.0
Max Unit
–
CLKs
Notes
(1)(2)(5)
–
CLKs
(1)(2)(5)
–
mS
(3)
–
CLKs
(1)(2)(5)
<5
ns
(4)
–
CLKs
(1)(2)(5)
–
CLKs
(1)(5)
–
CLKs
(1)(2)(5)
–
CLKs
(1)(2)
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is
added to the value in the table (where this note is referenced). See Figure 16 on page 27.
3. Since SCL and SDA are open-drain type outputs, which the PC8240 can only drive low, the time required for SCL or SDA to
reach a high level depends on external signal capacitance and pull-up resistor values.
26 PC8240
2149A–HIREL–05/02
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