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Table 3: Special function registers
* indicates SFRs that are bit addressable.
Name Description
SFR Bit functions and addresses
addr.
Reset
value
MSB
LSB Hex
Bit address E7
E6
E5
E4
E3
E2
E1
E0
ACC* Accumulator
E0H
00H
Bit address C7
C6
C5
C4
C3
C2
C1
C0
ADCON* A/D Control
C0h ENADC
ADCI
ADCS RCCLK AADR1 AADR0 02h
AUXR1 Auxiliary Function Register
A2h
KBF
BOD
BOI
LPEP
SRST
0
-
DPS 02h
Bit address F7
F6
F5
F4
F3
F2
F1
F0
B*
B register
F0h
00H
CMP1 Comparator 1 control register
ACh
-
-
CE1
CP1
CN1
OE1
CO1
CMF1 00H
CMP2 Comparator 2 control register
ADh
-
-
CE2
CP2
CN2
OE2
CO2
CMF2 00H
DAC0 A/D Result / Read
C5h
00H
DAC0 output value / Write
DAC1 DAC1 output value
C6h
00H
DIVM CPU clock divide-by-M control
95h
00H
DPTR Data pointer (2 bytes)
DPH Data pointer HIGH
83h
00H
DPL Data pointer LOW
82h
00H
Bit address CF
CE
CD
CC
CB
CA
C9
C8
I2CFG* I2C-bus configuration register
C8h/RD SLAVEN MASTRQ
0
TIRUN
-
-
CT1
CT0 00H
C8h/WR SLAVEN MASTRQ CLRTI TIRUN
-
-
CT1
CT0
Bit address DF
DE
DD
DC
DB
DA
D9
D8
I2CON* I2C-bus control register
D8h/RD RDAT
ATN
DRDY
ARL
STR
STP MASTER
-
80h
D8h/WR CXA
IDLE
CDR
CARL
CSTR
CSTP
XSTR
XSTP
I2DAT I2C-bus data register
D9h/RD RDAT
0
0
0
0
0
0
0
80h
D9h/WR XDAT
x
x
x
x
x
x
x
Bit address AF
AE
AD
AC
AB
AA
A9
A8
IEN0* Interrupt enable 0
A8h
EA
EWD
EBO
ES
ET1
EX1
ET0
EX0 00H
Bit address EF
EE
ED
EC
EB
EA
E9
E8
IEN1* Interrupt enable 1
E8h
ETI
-
EC1
EAD
-
EC2
EKB
EI2 00H