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P87LPC779

CMOS single-chip 8-bit 80C51 microcontroller with 128-byte data RAM, 8 kB OTP

Philips Electronics 

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

• Acknowledgment after each transferred byte.

• Multimaster bus.

• Arbitration between simultaneously transmitting masters without corruption of

serial data on bus.

The I2C-bus subsystem includes hardware to simplify the software required to drive

the I2C-bus. The hardware is a single bit interface which in addition to including the

necessary arbitration and framing error checks, includes clock stretching and a bus

timeout timer. The interface is synchronized to software either through polled loops or

interrupts. Refer to the application note AN422, in Section 4, entitled ‘Using the

8XC751 Microcontroller as an I2C-bus Master’ for additional discussion of the

87C77x I2C-bus interface and sample driver routines.

Six time spans are important in I2C-bus operation and are insured by timer I:

• The MINIMUM HIGH time for SCL when this device is the master.

• The MINIMUM LOW time for SCL when this device is a master. This is not very

important for a single-bit hardware interface like this one, because the SCL low

time is stretched until the software responds to the I2C-bus flags. The software

response time normally meets or exceeds the MIN LO time. In cases where the

software responds within MIN HI + MIN LO) time, timer I will ensure that the

minimum time is met.

• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.

• The MINIMUM SDA HIGH TO SDA LOW time between I2C-bus stop and start

conditions (4.7 ms, see I2C-bus specification).

• The MINIMUM SDA LOW TO SCL LOW time in a start condition.

The MAXIMUM SCL CHANGE time while an I2C-bus frame is in progress. A frame is

in progress between a start condition and the following stop condition. This time span

serves to detect a lack of software response on this device as well as external

I2C-bus problems. SCL ‘stuck low’ indicates a faulty master or slave. SCL ‘stuck high’

may mean a faulty device, or that noise induced onto the I2C-bus caused all masters

to withdraw from I2C-bus arbitration.

The first five of these times are 4.7 ms (see I2C-bus specification) and are covered by

the low order three bits of timer I. Timer I is clocked by the 87LPC77987 CPU clock.

Timer I can be pre-loaded with one of four values to optimize timing for different

oscillator frequencies. At lower frequencies, software response time is increased and

will degrade maximum performance of the I2C-bus. See special function register

I2CFG description for prescale values (CT0, CT1).

The MAXIMUM SCL CHANGE time is important, but its exact span is not critical. The

complete 10 bits of timer I are used to count out the maximum time. When I2C-bus

operation is enabled, this counter is cleared by transitions on the SCL pin. The timer

does not run between I2C-bus frames (i.e., whenever reset or stop occurred more

recently than the last start). When this counter is running, it will carry out after 1020 to

1023 machine cycles have elapsed since a change on SCL. A carry out causes a

hardware reset of the I2C-bus interface. In cases where the bus hang-up is due to a

lack of software response by this device, the reset releases SCL and allows I2C-bus

operation among other devices to continue.

9397 750 13213

Product data

Rev. 02 — 03 May 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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