Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 × 42 × 10)
Product specification
PLUS153B/D
LOGIC PROGRAMMING
The PLUS153B/D is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL™ and
CUPL™ design software packages also
support the PLUS153B/D architecture.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
PLUS153B/D logic designs can also be
generated using the program table entry
format, which is detailed on the following
page. This program table entry format is
supported by SNAP only.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-Party
Programmer/Software Support) of this data
handbook for additional information.
OUTPUT POLARITY – (B)
S
B
X
ACTIVE LEVEL
HIGH1
(NON–INVERTING)
CODE
H
AND ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
S
B
X
ACTIVE LEVEL
LOW
(INVERTING)
CODE
L
I, B
I, B
I, B
I, B
I, B
STATE
INACTIVE1, 2
P, D
CODE
O
OR ARRAY – (B)
P
S
STATE
I, B
P, D
CODE
H
P
STATE
I, B
S
P, D
CODE
L
STATE
DON’T CARE
P, D
CODE
–
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at “H” polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
Pn STATUS
ACTIVE1
CODE
A
Pn STATUS
INACTIVE
CODE
•
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either
I or B) are left intact.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
October 22, 1993
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